The Tongxin THA6 Gen 2 device family are Cortex-R52 based microcontrollers.

Flash Banks

R52 cores

THA6104

Flash bank	Base address	J-Link support	Flasher support	Loader
Flash bank	Base address	J-Link support	Flasher support	Name	Bank size
PFLASH0^[1]	0x08000000			Default	2 MB
PFLASH0 NVR^[2]	0x09800000			Default	16 KB
PFLASH1^[1]	0x08300000			Default	2 MB
PFLASH1 NVR^[2]	0x09804000			Default	16 KB
PFLASH0 (MBUS memory)^[2]	0x40400000			Default	2 MB
PFLASH0 NVR (MBUS memory)^[2]	0x41C00000			Default	16 KB
PFLASH1 (MBUS memory)^[2]	0x40700000			Default	2 MB
PFLASH1 NVR (MBUS memory)^[2]	0x41C04000			Default	16 KB
DFLASH0 (MBUS memory)^[1]	0x44000000			Default	512 KB
DFLASH0 NVR (MBUS memory)^[2]	0x44400000			Default	32 KB
PFLASH0 (MBUS device)^[2]	0x90400000			Default	2 MB
PFLASH0 NVR (MBUS device)^[2]	0x91C00000			Default	16 KB
PFLASH1 (MBUS device)^[2]	0x90700000			Default	2 MB
PFLASH1 NVR (MBUS device)^[2]	0x91C04000			Default	16 KB
DFLASH0 (MBUS device)^[2]	0x94000000			Default	256 KB
DFLASH0 NVR (MBUS device)^[2]	0x94400000			Default	32 KB

↑ ^1.0 ^1.1 ^1.2 Enabled by default
↑ ^2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 ^2.11 ^2.12 Disabled by default

THA6206

Flash bank	Base address	J-Link support	Flasher support	Loader
Flash bank	Base address	J-Link support	Flasher support	Name	Bank size
PFLASH0^[1]	0x08000000			Default	3 MB
PFLASH0 NVR^[2]	0x09800000			Default	16 KB
PFLASH1^[1]	0x08300000			Default	3 MB
PFLASH1 NVR^[2]	0x09804000			Default	16 KB
PFLASH0 (MBUS memory)^[2]	0x40400000			Default	3 MB
PFLASH0 NVR (MBUS memory)^[2]	0x41C00000			Default	16 KB
PFLASH1 (MBUS memory)^[2]	0x40700000			Default	3 MB
PFLASH1 NVR (MBUS memory)^[2]	0x41C04000			Default	16 KB
DFLASH0 (MBUS memory)^[1]	0x44000000			Default	512 KB
DFLASH0 NVR (MBUS memory)^[2]	0x44400000			Default	32 KB
PFLASH0 (MBUS device)^[2]	0x90400000			Default	3 MB
PFLASH0 NVR (MBUS device)^[2]	0x91C00000			Default	16 KB
PFLASH1 (MBUS device)^[2]	0x90700000			Default	3 MB
PFLASH1 NVR (MBUS device)^[2]	0x91C04000			Default	16 KB
DFLASH0 (MBUS device)^[2]	0x94000000			Default	512 KB
DFLASH0 NVR (MBUS device)^[2]	0x94400000			Default	32 KB

↑ ^1.0 ^1.1 ^1.2 Enabled by default
↑ ^2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 ^2.11 ^2.12 Disabled by default

THA6412

Note:

The THA6412 device is split into two logical devices in J-Link:

THA6412_R52_n (n=0,1,2,3):

Provides access to PFLASH and DFLASH memory.
Used for debugging and standard flash programming.
See #THA6412_R52 for supported flash banks.

THA6412_R52_n_NVR (n=0,1,2,3):

Provides access to NVR memory only.
Used exclusively for programming the NVR region.
See #THA6412_R52_NVR for supported flash banks.

THA6412_R52

Flash bank	Base address	J-Link support	Flasher support	Loader
Flash bank	Base address	J-Link support	Flasher support	Name	Bank size
PFLASH0^[1]	0x08000000			Default	3 MB
PFLASH1^[1]	0x08300000			Default	3 MB
PFLASH2^[1]	0x08600000			Default	3 MB
PFLASH3^[1]	0x08900000			Default	3 MB
PFLASH0 (MBUS memory)^[2]	0x40400000			Default	3 MB
PFLASH1 (MBUS memory)^[2]	0x40700000			Default	3 MB
PFLASH2 (MBUS memory)^[2]	0x40A00000			Default	3 MB
PFLASH3 (MBUS memory)^[2]	0x40D00000			Default	3 MB
DFLASH0 (MBUS memory)^[1]	0x44000000			Default	512 KB
PFLASH0 (MBUS device)^[2]	0x90400000			Default	3 MB
PFLASH1 (MBUS device)^[2]	0x90700000			Default	3 MB
PFLASH2 (MBUS device)^[2]	0x90A00000			Default	3 MB
PFLASH3 (MBUS device)^[2]	0x90D00000			Default	3 MB
DFLASH0 (MBUS device)^[2]	0x94000000			Default	512 KB

THA6412_R52_NVR

Flash bank	Base address	J-Link support	Flasher support	Loader
Flash bank	Base address	J-Link support	Flasher support	Name	Bank size
PFLASH0 NVR^[1]	0x09800000			Default	16 KB
PFLASH1 NVR^[1]	0x09804000			Default	16 KB
PFLASH2 NVR^[1]	0x09806000			Default	16 KB
PFLASH3 NVR^[1]	0x09808000			Default	16 KB
PFLASH0 NVR (MBUS memory)^[2]	0x41C00000			Default	16 KB
PFLASH1 NVR (MBUS memory)^[2]	0x41C04000			Default	16 KB
PFLASH2 NVR (MBUS memory)^[2]	0x41C08000			Default	16 KB
PFLASH3 NVR (MBUS memory)^[2]	0x41C0C000			Default	16 KB
DFLASH0 NVR (MBUS memory)^[1]	0x44400000			Default	32 KB
PFLASH0 NVR (MBUS device)^[2]	0x91C00000			Default	16 KB
PFLASH1 NVR (MBUS device)^[2]	0x91C04000			Default	16 KB
PFLASH2 NVR (MBUS device)^[2]	0x91C08000			Default	16 KB
PFLASH3 NVR (MBUS device)^[2]	0x91C0C000			Default	16 KB
DFLASH0 NVR (MBUS device)^[2]	0x94400000			Default	32 KB

↑ ^1.00 ^1.01 ^1.02 ^1.03 ^1.04 ^1.05 ^1.06 ^1.07 ^1.08 ^1.09 Enabled by default
↑ ^2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 ^2.11 ^2.12 ^2.13 ^2.14 ^2.15 ^2.16 ^2.17 Disabled by default

HSM

Flash bank	Base address	J-Link support	Flasher support	Loader
Flash bank	Base address	J-Link support	Flasher support	Name	Bank size
SFLASH^[1]	0x00000000			Default	512 KB
SFLASH (code attribute) (MBUS memory)^[2]	0x1C000000			Default	512 KB
SFLASH (memory attribute) (MBUS memory)^[2]	0x40180000			Default	512 KB
SFLASH (device attribute) (MBUS device)^[2]	0x90180000			Default	512 KB

↑ Enabled by default
↑ ^2.0 ^2.1 ^2.2 Disabled by default

Watchdog Handling

The device has a watchdog IWDT.
The watchdog is fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The THA6 family comes with a Cortex-R52 primary core and up to three Cortex-R52 secondary cores.

THA6104

Core	J-Link Support
Cortex-R52 CPU0
Cortex-R52 CPU1	^[1]
Cortex-M3 HSM

↑ Debugging is only possible when the cores are not operating in lockstep mode.

THA6206

Core	J-Link Support
Cortex-R52 CPU0
Cortex-R52 CPU1
Cortex-M3 HSM

THA6412

Core	J-Link Support
Cortex-R52 CPU0
Cortex-R52 CPU1
Cortex-R52 CPU2
Cortex-R52 CPU3
Cortex-M3 HSM

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

Secure Debug:
- Authentication levels EL1 and EL2 are supported.
- In case debug authentication is required, the 32-byte IDCode needs to be set via the command SetCPUConnectIDCODE <IDCode> before connecting to the device. If no IDCode is provided, the default IDCode (32x 0xFF) will be used.

J-Link>exec SetCPUConnectIDCODE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Halt timer configuration:
- Coresight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.

Reset

The device uses custom reset:
- Sets reset catch so that CPU is halted immediately after reset
- Performs reset via EDPRCR register
- Ensures that debug power domain and system power domain are powered up
- Powers core if necessary
- Enables debug mode if necessary
- Clears reset catch

Attach

Attach is supported

Secondary core(s)

Init/Setup

Secure Debug:
- Authentication levels EL1 and EL2 are supported.
- In case debug authentication is required, the 32-byte IDCode needs to be set via the command SetCPUConnectIDCODE <IDCode> before connecting to the device. If no IDCode is provided, the default IDCode (32x 0xFF) will be used.

J-Link>exec SetCPUConnectIDCODE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Halt timer configuration:
- Corsight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.

Reset

The device uses custom reset:
- Sets reset catch so that CPU is halted immediately after reset
- Performs reset via EDPRCR register
- Ensures that debug power domain and system power domain are powered up
- Powers core if necessary
- Enables debug mode if necessary
- Clears reset catch

Attach

Attach is supported

Evaluation Boards

Tongxin THA6206-KIT-V1.0

Example Application

Tongxin THA6206-KIT-V1.0

[FootNote1-1] 1.0 ^1.1 ^1.2 Enabled by default

[FootNote2-2] 2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 ^2.11 ^2.12 Disabled by default

[FootNote1-3] 1.0 ^1.1 ^1.2 Enabled by default

[FootNote2-4] 2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 ^2.11 ^2.12 Disabled by default

[FootNote1-5] 1.00 ^1.01 ^1.02 ^1.03 ^1.04 ^1.05 ^1.06 ^1.07 ^1.08 ^1.09 Enabled by default

[FootNote2-6] 2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 ^2.11 ^2.12 ^2.13 ^2.14 ^2.15 ^2.16 ^2.17 Disabled by default

[FootNote1-7] Enabled by default

[FootNote2-8] 2.0 ^2.1 ^2.2 Disabled by default

[FootNote3-9] Debugging is only possible when the cores are not operating in lockstep mode.

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Tongxin THA6 Gen 2

Contents

Flash Banks

R52 cores

THA6104

THA6206

THA6412

THA6412_R52

THA6412_R52_NVR

HSM

Watchdog Handling

Multi-Core Support

THA6104

THA6206

THA6412

Main core

Init/Setup

Reset

Attach

Secondary core(s)

Init/Setup

Reset

Attach

Evaluation Boards

Example Application

Navigation menu

Tongxin THA6 Gen 2

Flash Banks

R52 cores

THA6104

THA6206

THA6412

THA6412_R52

THA6412_R52_NVR

HSM

Watchdog Handling

Multi-Core Support

THA6104

THA6206

THA6412

Main core

Init/Setup

Reset

Attach

Secondary core(s)

Init/Setup

Reset

Attach

Evaluation Boards

Example Application

Navigation menu

Search