Tongxin THA6 Gen 2

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The Tongxin THA6 Gen 2 device family are Cortex-R52 based microcontrollers.

Flash Banks

THA6206

Flash Bank Base address J-Link Support Loader
Name Size
PFLASH0[1] 0x08000000 YES.png Default 3 MB
PFLASH0 NVR[2] 0x09800000 YES.png Default 16 KB
PFLASH1[1] 0x08300000 YES.png Default 3 MB
PFLASH1 NVR[2] 0x09804000 YES.png Default 16 KB
PFLASH0 (MBUS memory)[2] 0x40400000 YES.png Default 3 MB
PFLASH0 NVR (MBUS memory)[2] 0x41C00000 YES.png Default 16 KB
PFLASH1 (MBUS memory)[2] 0x40700000 YES.png Default 3 MB
PFLASH1 NVR (MBUS memory)[2] 0x41C04000 YES.png Default 16 KB
DFLASH0 (MBUS memory)[1] 0x44000000 YES.png Default 512 KB
DFLASH0 NVR (MBUS memory)[2] 0x44400000 YES.png Default 32 KB
PFLASH0 (MBUS device)[2] 0x90400000 YES.png Default 3 MB
PFLASH0 NVR (MBUS device)[2] 0x91C00000 YES.png Default 16 KB
PFLASH1 (MBUS device)[2] 0x90700000 YES.png Default 3 MB
PFLASH1 NVR (MBUS device)[2] 0x91C04000 YES.png Default 16 KB
DFLASH0 (MBUS device)[2] 0x94000000 YES.png Default 512 KB
DFLASH0 NVR (MBUS device)[2] 0x94400000 YES.png Default 32 KB
  1. ↑ 1.0 1.1 1.2 Enabled by default
  2. ↑ 2.00 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.09 2.10 2.11 2.12 Disabled by default

THA6412

Flash Bank Base address J-Link Support Loader
Name Size
PFLASH0[1] 0x08000000 YES.png Default 3 MB
PFLASH0 NVR[2] 0x09800000 YES.png Default 16 KB
PFLASH1[1] 0x08300000 YES.png Default 3 MB
PFLASH1 NVR[2] 0x09804000 YES.png Default 16 KB
PFLASH2[1] 0x08600000 YES.png Default 3 MB
PFLASH2 NVR[2] 0x09806000 YES.png Default 16 KB
PFLASH3[1] 0x08900000 YES.png Default 3 MB
PFLASH3 NVR[2] 0x09808000 YES.png Default 16 KB
PFLASH0 (MBUS memory)[2] 0x40400000 YES.png Default 3 MB
PFLASH0 NVR (MBUS memory)[2] 0x41C00000 YES.png Default 16 KB
PFLASH1 (MBUS memory)[2] 0x40700000 YES.png Default 3 MB
PFLASH1 NVR (MBUS memory)[2] 0x41C04000 YES.png Default 16 KB
PFLASH2 (MBUS memory)[2] 0x40A00000 YES.png Default 3 MB
PFLASH2 NVR (MBUS memory)[2] 0x41C08000 YES.png Default 16 KB
PFLASH3 (MBUS memory)[2] 0x40D00000 YES.png Default 3 MB
PFLASH3 NVR (MBUS memory)[2] 0x41C0C000 YES.png Default 16 KB
DFLASH0 (MBUS memory)[1] 0x44000000 YES.png Default 512 KB
DFLASH0 NVR (MBUS memory)[2] 0x44400000 YES.png Default 32 KB
PFLASH0 (MBUS device)[2] 0x90400000 YES.png Default 3 MB
PFLASH0 NVR (MBUS device)[2] 0x91C00000 YES.png Default 16 KB
PFLASH1 (MBUS device)[2] 0x90700000 YES.png Default 3 MB
PFLASH1 NVR (MBUS device)[2] 0x91C04000 YES.png Default 16 KB
PFLASH2 (MBUS device)[2] 0x90A00000 YES.png Default 3 MB
PFLASH2 NVR (MBUS device)[2] 0x91C08000 YES.png Default 16 KB
PFLASH3 (MBUS device)[2] 0x90D00000 YES.png Default 3 MB
PFLASH3 NVR (MBUS device)[2] 0x91C0C000 YES.png Default 16 KB
DFLASH0 (MBUS device)[2] 0x94000000 YES.png Default 512 KB
DFLASH0 NVR (MBUS device)[2] 0x94400000 YES.png Default 32 KB
  1. ↑ 1.0 1.1 1.2 1.3 1.4 Enabled by default
  2. ↑ 2.00 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.09 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 Disabled by default

Watchdog Handling

  • The device has a watchdog IWDT.
  • The watchdog is fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The THA6 family comes with a Cortex-R52 primary core and up to three Cortex-R52 secondary cores.

THA6412

Core J-Link Support
Cortex-R52 CPU0 YES.png
Cortex-R52 CPU1 YES.png
Cortex-R52 CPU2 YES.png
Cortex-R52 CPU3 YES.png
Cortex-M3 HSM YES.png

THA6206

Core J-Link Support
Cortex-R52 CPU0 YES.png
Cortex-R52 CPU1 YES.png
Cortex-M3 HSM YES.png

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

  • Secure Debug:
    • Authentication levels EL1 and EL2 are supported.
    • Only the default password (all bytes set to 0xFF) is supported. If you need to unlock the device using a custom password, please contact us through our support ticket system.
  • Halt timer configuration:
    • Corsight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.

Reset

  • The device uses custom reset:
    • Sets reset catch so that CPU is halted immediately after reset
    • Performs reset via EDPRCR register
    • Ensures that debug power domain and system power domain are powered up
    • Powers core if necessary
    • Enables debug mode if necessary
    • Clears reset catch

Attach

  • Attach is supported

Secondary core(s)

Init/Setup

  • Secure Debug:
    • Authentication levels EL1 and EL2 are supported.
    • Only the default password (all bytes set to 0xFF) is supported. If you need to unlock the device using a custom password, please contact us through our support ticket system.
  • Halt timer configuration:
    • Corsight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.

Reset

  • The device uses custom reset:
    • Sets reset catch so that CPU is halted immediately after reset
    • Performs reset via EDPRCR register
    • Ensures that debug power domain and system power domain are powered up
    • Powers core if necessary
    • Enables debug mode if necessary
    • Clears reset catch

Attach

  • Attach is supported

Evaluation Boards

Example Application

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