Tongxin THA6 Gen 2: Difference between revisions
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{{:Template:FlashBankTableRow | BankName=PFLASH0<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=PFLASH0<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=3 MB }} | {{:Template:FlashLoader | Name=Default | Size=3 MB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=PFLASH0 NVR<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x09800000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=16 KB }} | |||
}} | }} | ||
{{:Template:FlashBankTableRow | BankName=PFLASH1<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08300000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=PFLASH1<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08300000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=3 MB }} | {{:Template:FlashLoader | Name=Default | Size=3 MB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=PFLASH1 NVR<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x09804000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=16 KB }} | |||
}} | }} | ||
{{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=3 MB }} | {{:Template:FlashLoader | Name=Default | Size=3 MB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=PFLASH0 NVR (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x41C00000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=16 KB }} | |||
}} | }} | ||
{{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=3 MB }} | {{:Template:FlashLoader | Name=Default | Size=3 MB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=PFLASH1 NVR (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x41C04000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=16 KB }} | |||
}} | }} | ||
{{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS memory)<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x44000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS memory)<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x44000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=512 KB }} | {{:Template:FlashLoader | Name=Default | Size=512 KB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=DFLASH0 NVR (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x44400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=32 KB }} | |||
}} | }} | ||
{{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=3 MB }} | {{:Template:FlashLoader | Name=Default | Size=3 MB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=PFLASH0 NVR (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x91C00000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=16 KB }} | |||
}} | }} | ||
{{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=3 MB }} | {{:Template:FlashLoader | Name=Default | Size=3 MB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=PFLASH1 NVR (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x91C04000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=16 KB }} | |||
}} | }} | ||
{{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x94000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | {{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x94000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | ||
{{:Template:FlashLoader | Name=Default | Size=512 KB }} | {{:Template:FlashLoader | Name=Default | Size=512 KB }} | ||
}} | |||
{{:Template:FlashBankTableRow | BankName=DFLASH0 NVR (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x94400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= | |||
{{:Template:FlashLoader | Name=Default | Size=32 KB }} | |||
}} | }} | ||
}} | }} | ||
<references /> | <references /> | ||
==Watchdog Handling== | ==Watchdog Handling== |
Revision as of 09:37, 24 June 2025
The Tongxin THA6 Gen 2 device family are Cortex-R52 based microcontrollers.
Flash Banks
Flash Bank | Base address | J-Link Support | Loader | |
---|---|---|---|---|
Name | Size | |||
PFLASH0[1] | 0x08000000 | ![]() |
Default | 3 MB |
PFLASH0 NVR[2] | 0x09800000 | ![]() |
Default | 16 KB |
PFLASH1[1] | 0x08300000 | ![]() |
Default | 3 MB |
PFLASH1 NVR[2] | 0x09804000 | ![]() |
Default | 16 KB |
PFLASH0 (MBUS memory)[2] | 0x40400000 | ![]() |
Default | 3 MB |
PFLASH0 NVR (MBUS memory)[2] | 0x41C00000 | ![]() |
Default | 16 KB |
PFLASH1 (MBUS memory)[2] | 0x40700000 | ![]() |
Default | 3 MB |
PFLASH1 NVR (MBUS memory)[2] | 0x41C04000 | ![]() |
Default | 16 KB |
DFLASH0 (MBUS memory)[1] | 0x44000000 | ![]() |
Default | 512 KB |
DFLASH0 NVR (MBUS memory)[2] | 0x44400000 | ![]() |
Default | 32 KB |
PFLASH0 (MBUS device)[2] | 0x90400000 | ![]() |
Default | 3 MB |
PFLASH0 NVR (MBUS device)[2] | 0x91C00000 | ![]() |
Default | 16 KB |
PFLASH1 (MBUS device)[2] | 0x90700000 | ![]() |
Default | 3 MB |
PFLASH1 NVR (MBUS device)[2] | 0x91C04000 | ![]() |
Default | 16 KB |
DFLASH0 (MBUS device)[2] | 0x94000000 | ![]() |
Default | 512 KB |
DFLASH0 NVR (MBUS device)[2] | 0x94400000 | ![]() |
Default | 32 KB |
Watchdog Handling
- The device has a watchdog IWDT.
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- Secure Debug:
- Authentication levels EL1 and EL2 are supported.
- Only the default password (all bytes set to 0xFF) is supported. If you need to unlock the device using a custom password, please contact us through our support ticket system.
Reset
- The device uses custom reset:
- Sets reset catch so that CPU is halted immediately after reset
- Performs reset via EDPRCR register
- Ensures that debug power domain and system power domain are powered up
- Powers core if necessary
- Enables debug mode if necessary
- Clears reset catch
Halt Timer Configuration
- The device supports halt timer configuration.
- The following timers are halted simultaneously with the R52 cores (STM, IWDT, SAFEWDT, CPUWDTn, BASETIMERn).