Tongxin THA6 Gen 2: Difference between revisions
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| Line 49: | Line 49: | ||
=== Halt Timer Configuration === | === Halt Timer Configuration === | ||
* The device supports halt timer configuration. | * The device supports halt timer configuration. | ||
* The | * The following timers are halted simultaneously with the R52 cores (STM, IWDT, SAFEWDT, CPUWDTn, BASETIMERn). | ||
==Evaluation Boards== | ==Evaluation Boards== | ||
Revision as of 12:01, 15 May 2025
The Tongxin THA6 Gen 2 device family are Cortex-R52 based microcontrollers.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| PFLASH0[1] | 0x08000000 | 
|
Default | 3 MB |
| PFLASH1[1] | 0x08300000 |
|
Default | 3 MB |
| PFLASH0 (MBUS memory)[2] | 0x40400000 |
|
Default | 3 MB |
| PFLASH1 (MBUS memory)[2] | 0x40700000 |
|
Default | 3 MB |
| DFLASH0 (MBUS memory)[1] | 0x44000000 |
|
Default | 512 KB |
| PFLASH0 (MBUS device)[2] | 0x90400000 |
|
Default | 3 MB |
| PFLASH1 (MBUS device)[2] | 0x90700000 |
|
Default | 3 MB |
| DFLASH0 (MBUS device)[2] | 0x94000000 |
|
Default | 512 KB |
Watchdog Handling
- The device has a watchdog IWDT.
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses custom reset:
- Sets reset catch so that CPU is halted immediately after reset
- Performs reset via EDPRCR register
- Ensures that debug power domain and system power domain are powered up
- Powers core if necessary
- Enables debug mode if necessary
- Clears reset catch
Halt Timer Configuration
- The device supports halt timer configuration.
- The following timers are halted simultaneously with the R52 cores (STM, IWDT, SAFEWDT, CPUWDTn, BASETIMERn).