Tongxin THA6 Gen 2: Difference between revisions

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(Created page with "Category:Device families The '''Tongxin THA6 Gen 2''' device family are Cortex-R52 based microcontrollers. __TOC__ ==Flash Banks== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankName=PFLASH0<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= {{:Template:FlashLoader | Name=Default | Size=3 MB }} }} {{:Template:FlashBankTableRow | BankName=PFLASH1<ref name="FootNote1" >Ena...")
 
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==ECC RAM [OPTIONAL]==
*Describe ECC RAM restriction here.
==Vector Table Remap [OPTIONAL]==
*Describe Vector Table Remap here..


==Watchdog Handling==
==Watchdog Handling==
*The device does not have a watchdog.
*The device has a watchdog IWDT.  
*The device has a watchdog [WATCHDOGNAME].  
*The watchdog is fed during flash programming.
*The watchdog is fed during flash programming.
*If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
*The watchdog can be configured in normal or window mode.
** If it is configured in normal mode the watchdog is feed during flash programming.
** If it is configured in window mode the watchdog is feed during flash programming.
** If it is configured in window mode the watchdog is '''not''' feed.
==Multi-Core Support [OPTIONAL]==
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
The [DeviceFamily]family comes with a variety of multi-core options.<br>
Some devices from this family feature a secondary core which is disabled after reset / by default.<br>
Some of the are available with enabled ''lockstep'' mode, only. <br>
{| class="seggertable"
|-
! Core || J-Link Support
|-
| [CORE_NAME] || style="text-align:center;"| {{YES}} / {{NO}}
|}
In below, the debug related multi-core behavior of the J-Link is described for each core:
===Main core===
====Init/Setup====
*Initializes the ECC RAM, see [[XXX | XXX]]
*Enables debugging
====Reset====
*Device specific reset is performed, see [[XXX | XXX]]
====Attach====
*Attach is not supported because the J-Link initializes certain RAM regions by default
===Secondary core(s)===
====Init/Setup====
*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
*If the secondary core is not enabled yet, it will be enabled / release from reset
====Reset====
No reset is performed.
====Attach====
*Attach is supported / desired


==Device Specific Handling==
==Device Specific Handling==
===Connect===
===Reset===
===Reset===
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
*The device uses custom reset:
*The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]].
**Sets reset catch so that CPU is halted immediately after reset
*The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]].
**Performs reset via EDPRCR register
*The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]].
**Ensures that debug power domain and system power domain are powered up
*The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]].
**Powers core if necessary
*The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]].
**Enables debug mode if necessary
*The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]].
**Clears reset catch
*The device uses custom reset:.....
 
==Limitations==
===Dual Core Support===
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
===Attach===
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
===Security===


==Evaluation Boards==
==Evaluation Boards==
*[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]]
*[[Tongxin THA6206-KIT-V1.0]]


==Example Application==
==Example Application==
*[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]]
*[[Tongxin THA6206-KIT-V1.0#Example_Project | Tongxin THA6206-KIT-V1.0]]
 
== Tracing ==
The following trace example projects are available:
* [Link to Board Article1]
* [Link to Board Article2]
* ...

Revision as of 16:56, 11 March 2025

The Tongxin THA6 Gen 2 device family are Cortex-R52 based microcontrollers.

Flash Banks

Flash Bank Base address J-Link Support Loader
Name Size
PFLASH0[1] 0x08000000 YES.png Default 3 MB
PFLASH1[1] 0x08300000 YES.png Default 3 MB
PFLASH0 (MBUS memory)[2] 0x40400000 YES.png Default 3 MB
PFLASH1 (MBUS memory)[2] 0x40700000 YES.png Default 3 MB
DFLASH0 (MBUS memory)[1] 0x44000000 YES.png Default 512 KB
PFLASH0 (MBUS device)[2] 0x90400000 YES.png Default 3 MB
PFLASH1 (MBUS device)[2] 0x90700000 YES.png Default 3 MB
DFLASH0 (MBUS device)[2] 0x94000000 YES.png Default 512 KB
  1. ↑ 1.0 1.1 1.2 Enabled by default
  2. ↑ 2.0 2.1 2.2 2.3 2.4 Disabled by default


Watchdog Handling

  • The device has a watchdog IWDT.
  • The watchdog is fed during flash programming.

Device Specific Handling

Reset

  • The device uses custom reset:
    • Sets reset catch so that CPU is halted immediately after reset
    • Performs reset via EDPRCR register
    • Ensures that debug power domain and system power domain are powered up
    • Powers core if necessary
    • Enables debug mode if necessary
    • Clears reset catch

Evaluation Boards

Example Application

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