View source for TI AM261x

[[Category:Device families]]
The '''TI AM261x''' are Arm Cortex-R5F-based MCUs with up to 2 cores for real-time control, safety and security applications.
__TOC__

==Flash Banks==
{{:Template:FlashBankTable
| FlashBanks=
{{:Template:FlashBankTableRow | BankName=QSPI Flash | BaseAddress=0x60000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=128 MB }}
}}
}}

==ECC RAM==
*If the DevBoot mode is selected, TCMA RAM will be initialized for correct ECC operation during the connect phase.

==Watchdog Handling==
*The device has two watchdogs: WWDT0 and WWDT1: one for each core.
*During flash programming the only WWDT0(core 0) is fed, as the core should not access the watchdog of another core.

==Multi-Core Support==
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
The AM261x family comes with a variety of multi-core options.<br>
Some devices from this family feature a secondary core which function as a diagnostic core(Lockstep mode) by default.<br>
When connecting to a secondary core, it will be switched to the Dual-core mode. <br>
{| class="seggertable"
|-
! Core || J-Link Support
|-
| Arm Cortex-R5F_0 || style="text-align:center;"| {{YES}}
|-
| Arm Cortex-R5F_1 || style="text-align:center;"| {{YES}}
|}

In below, the debug related multi-core behavior of the J-Link is described for each core:
===Main core===
====Init/Setup====
*Initializes the ECC TCMA RAM only in DevBoot mode.
====Reset====
*In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a [[J-Link_script_files | J-Link script file]].
====Attach====
*Attach is not supported when the device is in the DevBoot mode and TCMA RAM is used(ECC initialization is performed).
===Secondary core(s)===
====Init/Setup====
*Initializes the ECC TCMA RAM only in DevBoot mode.
*Disables Lockstep mode.
====Reset====
*No reset is performed.
====Attach====
*Attach is not supported when the device is in the DevBoot mode and TCMA RAM is used(ECC initialization is performed).

==Device Specific Handling==
===Connect===
===Reset===
*The device reset is not performed, as it requires multi-core and boot-loader handling.

==Evaluation Boards==
*[[TI_AM261x_SOM|TI AM261x SOM]]

==Example Application==
*[[TI_AM261x_SOM#Example_Project | TI AM261x SOM]]