View source for Nordic Semiconductor nRF54Lxx

[[Category:Device families]]
The '''Nordic Semiconductor nRF54L''' are ultra low-power multiprotocol wireless System-on-Chip (SoC) supporting Bluetooth Low Energy, Bluetooth mesh, Thread, and Matter technologies.
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==Flash Banks==
===nRF54L15===
{{:Template:FlashBankTable
| FlashBanks=
{{:Template:FlashBankTableRow | BankName=RRAM | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Internal flash | Size=1524 KB}}
}}
{{:Template:FlashBankTableRow | BankName=UICR | BaseAddress=0x00FFD000 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
{{:Template:FlashBankTableRow | BankName=OTP | BaseAddress=0x00FFD500 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
}}

==Watchdog Handling==
*The device has two watchdogs WDT30 and WDT31. 
*The watchdogs are fed during flash programming.

==Multi-Core Support==
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
The nRF54Lxx family comes with a variety of multi-core options.<br>

{| class="seggertable"
|-
! Core || J-Link Support
|-
| Cortex-M33 || style="text-align:center;"| {{YES}}
|-
| RISC-V RV32 || style="text-align:center;"| {{NO}}
|}

In below, the debug related multi-core behavior of the J-Link is described for each core:
===Main core===
====Attach====
*Attach is supported.

==Device Specific Handling==
===Reset===
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].

==Limitations==
===Dual Core Support===
The nRF54Lxx devices feature a second RISC-V core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
===Security===
The nRF54Lxx Series uses special debug locking mechanism. To gain access to debugging features the following steps should be performed: 1) UICR registers should be configured to enable debug port. 2) User application should set corresponding registers to open access to debug port.
Optionally J-Link can perform a full chip erase, to temporarily reopen debug access until next power reset. 

==Evaluation Boards==
*[[Nordic_nRF54L15-PDK | Nordic Semiconductor nRF54L15-PDK]]

==Example Application==
*[[Nordic_nRF54L15-PDK#Example_Project | Nordic Semiconductor nRF54L15-PDK]]