Tongxin THA8 Gen 3

The Tongxin THA8 Gen 3 device family are Cortex-R52+ based microcontrollers.

Flash Banks

R52

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
PFLASH	0x28000000		Default	20 MB
PFLASH NVR	0x2D400000		Default	1536 KB
DFLASH	0x51800000		Default	1 MB
DFLASH NVR	0x51900000		Default	128 KB

HSM

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
SPFLASH	0x24100000		Default	1 MB
SDFLASH	0x24200000		Default	1 MB
SPFLASH NVR	0x24400000		Default	128 KB
SDFLASH NVR	0x24480000		Default	128 KB

Watchdog Handling

• The device has a watchdog.
• The watchdog is fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The THA8 family features a Cortex-R52 primary core and five Cortex-R52 secondary cores, as well as three M52 cores.

Core	J-Link Support
Cortex-R52 CPU0
Cortex-R52 CPU1
Cortex-R52 CPU2
Cortex-R52 CPU3
Cortex-R52 CPU4
Cortex-R52 CPU5
Cortex-M52 HSM
Cortex-M52 DME
Cortex-M52 DSPH

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core (R52 CPU0)

Reset

• The device uses custom reset:
  • Sets reset catch so that CPU is halted immediately after reset
  • Performs Warm reset via EDPRCR register
  • Initalizes the RAM

Attach

• Attach is supported

Secondary cores (R52 CPU1-5)

Init/Setup

• The core is started via AXI-AP

Reset

• The device uses custom reset:
  • Sets reset catch so that CPU is halted immediately after reset
  • Performs Warm reset via EDPRCR register
  • The core is started via AXI-AP
  • Initalizes the RAM

Attach

• Attach is supported

M52 cores (HSM, DME, DSPH)

Init/Setup

• The core is started via AXI-AP

Reset

• The device uses the standard Cortex-M reset sequence J-Link_Reset_Strategies#Strategies_for_Cortex-M_devices.

Attach

• Attach is supported