Template:ST SR6Px MultiCoreSupport CL0 4Cores

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The {{{1}}} family comes with {{{2}}} Cortex-R52 and {{{3}}} Cortex-M4 cores. Some of them are available with enabled split lock mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Cluster 0 Core 0 Cortex-R52

Init/Setup

• WDT is enabled by default. If it is enabled, it will be disabled.

Reset

• ARMv8-R Reset is performed like described here.
• Initializes 256KB ECC RAM starting at 0x60000000
• WDT is enabled by default. If it is enabled, it will be disabled.

Attach

• Attach is not supported, because of ECC RAM initialization.
• Attach can be done by selecting Cortex-R52 as target device with the restriction that flash breakpoints are not available.

Cluster 0 Core 1 Cortex-R52

Init/Setup

• WDT is enabled by default. If it is enabled, it will be disabled.
• If core is not enabled, it will be enabled (set to DRUN condition).

Reset

• ARMv8-R Reset is performed like described here.

Attach

• Attach is supported

Cluster 0 Core 2 Cortex-R52 (if available)

Init/Setup

• WDT is disabled
• If core is not enabled, it will be enabled (set to DRUN condition).
• To connect to this core, bit split_lock has to be set to 1 on DCF Global_CONF.

Reset

• ARMv8-R Reset is performed like described here.

Attach

• Attach is supported

Cluster 0 Core 3 Cortex-R52 (if available)

Init/Setup

• WDT is disabled
• If core is not enabled, it will be enabled (set to DRUN condition).
• To connect to this core, bit split_lock has to be set to 1 on DCF Global_CONF.

Reset

• ARMv8-R Reset is performed like described here.

Attach

• Attach is supported