Template:ST SR6Px MultiCoreSupport

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Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The {{{1}}} family comes with up to 10 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Cortex-R52 Cluster 0 Core 0

Init/Setup

  • WDT is enabled by default. If it is enabled, it will be disabled.

Reset

  • ARMv8-R Reset is performed like described here.

{{{2}}}

  • Initializes 256KB ECC RAM starting at 0x60000000
  • WDT is enabled by default. If it is enabled, it will be disabled.

Attach

    • Attach is supported if WorkRAM init is skipped.

Cortex-R52 Cluster 0 Core 1

Init/Setup

  • WDT is enabled by default. If it is enabled, it will be disabled.
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cortex-R52 Cluster 1 Core 0 (if available)

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cortex-R52 Cluster 1 Core 1 (if available)

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cortex-R52 Cluster 2 Core 0

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

DSPH Core

Init/Setup

  • none

Reset

  • Cortex-M Typ 0 normal reset is performed like described here.

Attach

  • Attach is supported

DME Core

Init/Setup

  • none

Reset

  • Cortex-M Typ 0 normal reset is performed like described here.

Attach

  • Attach is supported

HSM Core

Init/Setup

  • Initializes 64KB ECC RAM starting at 0x00800000
  • SWT is enabled by default. If it is enabled, it will be disabled.

Reset

  • Functional reset is executed.

Attach

  • Attach is supported if WorkRAM init is skipped.