Template:JLinkResetStrategiesCortexAR

J-Link supports a default reset strategy for the {{{1}}} cores. The following reset strategy is available via JTAG and in SWD as target interface. It halts the CPU after the reset.

Note:

It is recommended that the correct device is selected in the debugger so the debugger can pass the device name to the J-Link Software which makes it possible for J-Link to detect what is the best reset strategy for the device.

Moreover, we recommend that the debugger uses reset type 0 to allow J-Link to dynamically select what reset is the best for the connected device.

Type 0: normal

J-Link sets Vector Catch Enable in Vector Catch Register and DBGNOPWRDWN in Device Power Down and Reset Control Register. Afterwards, a reset is triggered via the reset pin with a (by default) 20 ms high phase. After the reset signal, J-Link allows a 100 ms delay to let the core boot.