TI MSPM33

The Marvell 88MC200 are microcontrollers based on the ARM Cortex-M33 core.

Flash Banks

Flash Bank	Base address	Size	J-Link Support
Internal Flash	0x00000000	Up to 1024 KB
Data Flash	0x80000000	32 KB
NONMAIN	0x80100000	16 KB
FACTORY	0x80110000	8 KB

ECC flash

The flash is ECC protected.

• When programming code with J-Link, the device flash controller is set to automatically program the correct ECC values.
• Manual ECC programming is currently not supported by J-Link.

ECC RAM

The device has SRAM with ECC that is initialized on connect.

Watchdog Handling

The device has two watchdogs:

• IWDT is turned off during flash programming and turned back on afterwards if enabled.
• WWDT is fed during flash programming but there is one restriction: As the watchdog counter cannot be read directly, flash programming is only supported for devices where WWDT is not running in window mode.

Device Specific Handling

Connect

Some device specific debug bits are set which prevents the device to enter sleep mode and allows debugging of applications which make use of low power modes.

Reset

A device specific reset is performed for this device because the peripherals are not reset when executing the Cortex-M default reset. A SYSRST is executed via the device specific SYSCTL register instead. The bootloader runs first and execution is halted when jumping to the application.