Synopsys ARC-V RHX-110-FS
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The Synopsys ARC-V RHX-110-FS are proprietary RISC-V processor cores developed by Synopsys and offered as licensable IP for integration into custom SoCs and other silicon designs by third-party semiconductor vendors.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| JTAG[1] |  |
|
Device specific handling
Although the cores are based on the RISC-V architecture, the final implementation and available features (for example FPU) depend on the configuration selected by the silicon vendor. So refer to the device manual integrating this core about the supported features especially regarding the debug interface.
Cache handling
Those devices can feature an embedded L1-cache. J-Link automatically supports invalidating the I-cache in the core.
Reset
- The core uses normal RISC-V reset, no special handling necessary, like described here.
Attach
Attach is a debugging feature which exclusively applies to J-Link and J-Trace and does not apply to Flasher.
- Attach is generally available