ST STM32N6
The ST STM32N6 devices are Cortex-M55 based general-purpose MCUs.
Flash Banks
Internal Flash
STM32N6 devices do not have internal flash memory for code, but OTP memory in the BSEC peripheral. The OTP area is divided in 3 regions (lower, mid and upper).
Note: Some OTP locations are already used by the vendor and cannot be changed. Please refer to the reference manual for your STM32N6 device for usable OTP locations.
| Flash Bank | Base address | Size | JLink Support |
|---|---|---|---|
| OTP area (STM32N6x7) | 0x46009000 | 376 words (1504 Bytes) | 
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for STM32N6. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| STM32N657xx | 0x70000000 | 256 MB |
|
Watchdog Handling
- The device has two watchdogs IWDG and WWDG.
- The watchdogs are fed during flash programming.
- If the IWDG watchdog is running with activated window option, it is disabled while flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Evaluation Boards
Tracing
The following trace example projects are available: