ST SR6P3
The ST SR6P3xx are Stellar P series microcontroler, which inlcude 3 Cortex-R52+ and 3 Cortex-M4.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| RWW Partition 0 | 0x28000000 | 2816 KB | 
|
| RWW Partition 1 | 0x28400000 | 2816 KB |
|
| RWW Partition 2 | 0x28800000 | 1024 KB |
|
| RWW Partition 3 | 0x28900000 | 1024 KB |
|
| EEPROM / RWW 4 | 0x29E00000 | 128 KB |
|
| UTEST / RWW 0 | 0x29F80000 | 32 KB |
|
| Boot Code Sector / RWW 0 | 0x29FB8000 | 16 KB | 
|
| HSM Code A / RWW 5 | 0x00000000 | 256 KB |
|
| HSM Code B / RWW 6 | 0x00100000 | 256 KB |
|
| HSM Data / RWW 7 | 0x003A0000 | 128 KB |
|
| HSM UT / RWW 11 | 0x0037C000 | 16 KB |
|
Flash programming
Flash programming of above listed flash regions is done through Cluster0 Core0 (Cortex-R52), except the HSM regions.
These are programmed via the HSM core.
The flash controller has no explicit erase function.
When reprogramming flash an explicit erase before programming is not necessary. Already programmed flash can be directly reprogrammed.
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary. Please refer to the reference Manual. ECC RAM initialization is done for Cluster 0 Core 0, see below.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6P3 family comes with 3 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled split lock mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cluster 0 Core 0 Cortex-R52
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
Reset
- ARMv8-R Reset is performed like described here.
- Initializes 256KB ECC RAM starting at 0x60000000
- WDT is enabled by default. If it is enabled, it will be disabled.
Attach
- Attach is supported if WorkRAM init is skipped.
Cluster 0 Core 1 Cortex-R52
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cluster 1 Core 0 Cortex-R52
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
DSPH Core Cortex-M4
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
DME Core Cortex-M4
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
HSM Core
Init/Setup
- Initializes 64KB ECC RAM starting at 0x00800000
- SWT is enabled by default. If it is enabled, it will be disabled.
Reset
- Functional reset is executed.
Attach
- Attach is supported if WorkRAM init is skipped.
Device Specific Handling
Reset
- Depending on connected core, different resets are performed, see above.