Renesas RZ/T2M-RSK

This article describes specifics for the Renesas RZ/T2M-RSK evaluation board.

Minimum requirements

• J-Link software V7.68 or later

Preparing for J-Link

• Connect the J-Link to the debug header (J13 or J20)
• Power the board via USB C (CN5) or external power supply / power jack (CN6)
• Verify the Connection with e.g. J-Link Commander. The output should look as follows:

NOR flash programming

Board Preparation

1. Check whether SW4 on RZ/T2M RSK board is set as 16bit bus boot mode(NOR flash):
   <SW4> (16bit bus boot mode (NOR flash))
   1-ON; 2-OFF; 3-ON
   <SW6> (16bit bus boot mode (NOR flash))
   1-ON
2. Power on reset the RZ/T2M RSK board

Test Procedure

1. Start J-Link Commander
   JLink.exe -device R9A07G075M0 -if SWD -speed 12000 -autoconnect 1
2. Enter the following commands
   r
   loadfile 1MB_TestData.bin,0x70000000
3. Repeat the loadfile sequence several times
   Expected result: Programming skipped
4. Enter the following commands
   r
   exec setcomparemode 0
   loadfile 1MB_TestData.bin,0x70000000
5. Repeat the loadfile sequence several times
   Expected result: Programming will be executed each time because compare step is skipped

Example Project

TBD

SETUP

TBD

Tracing on Renesas RZ/T2M

This section describes how to get started with trace on the Renesas RZ/T2M MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

Some of the examples are shipped with a compiled .JLinkScriptfile (extension .pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Minimum requirements

In order to use trace on the Renesas RZ/T2M MCU devices, the following minimum requirements have to be met:

• J-Link software version V8.80 or later
• Ozone V3.40c or later (if streaming trace and / or the sample project from below shall be used)
• J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
• J-Link Plus V12 or later for TMC/ETB trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V8.24. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

The project below has been tested with the minimum requirements mentioned above and a RZ/T2M-RSK.

• Example project: Renesas_RZ_T2M_TraceExample.zip

Streaming trace

Open the *_TracePins.jdebug project contained in the example project in Ozone.

Trace buffer (TMC/ETB)

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Tested Hardware

RZ/T2M-RSK

Specifics/Limitations

The board needs to be set up so trace pins are available. Trace pins are only connected to connector CN9. You will need the following adapter for the connection: https://www.segger.com/products/debug-probes/j-trace/accessories/adapters/j-trace-mictor-38-adapter/
Additionally on switch SW6 switch 1 must be set to off. For more detailed information see the boards reference manual.

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time