Renesas RZ/N1D

The Renesas RZ/N1 are multicore devices consisting of one Cortex-M3 and up to three Cortex-A7.

Flash Banks

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.

Bank	Base address	Maximum size	Supported
QSPI1	0x10000000	256 MB

Watchdog Handling

• The device has a watchdog WDOGCM3.
• If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The RZ/N1 family comes with a Cortex-M3 primary core and up to three Cortex-A7 secondary cores.

Core	J-Link Support
Cortex-M3
Cortex-A7
Cortex-A7 CPU0
Cortex-A7 CPU1

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core (Cortex-M3)

Init/Setup

• Releases Cortex-M3 from reset if necessary
• Enables debugging

Reset

• Device specific reset through PWRCTRL_CM3 register is performed.

Secondary core(s)

Init/Setup

• Enables debugging.

Reset

• The device uses Cortex-A reset, no special handling necessary, like described here.