Renesas RZ/G3SE
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The Renesas RZ/G3SE series includes a Cortex-A55 as well as a Cortex-M33.
Flash Banks
Internal Flash
The device does not feature internal flash.
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| External QSPI flash (secure) | 0x80000000 | 256 MB |
|
| External QSPI flash (non-secure) | 0x90000000 | 256 MB |
|
CM33
Init/Setup
If the CM33 is held in reset, J-Link releases the core from reset and let it execute a while (1) code located at 0x000A0000.
Reset
- Device specific reset is performed:
J-Link executes the reset sequence specified by Renesas. This reset is basically a reset via reset pin followed by the release CM33 from reset sequence. After reset, the CPU is halted in the while (1) loop located at 0x00120000.
Attach
- Attach is possible in case of the CM33 core is clocked and released from reset
Cortex-A55
J-Link does not support the Cortex-A55.