Renesas RZ/A1H

The Renesas RZ/A1H is are high-end 32-bit CPUs based on the Cortex-A9 core.

Flash Banks

Flash Bank	Base address	Size	J-Link Support
External QSPI flash	0x18000000	Up to 64MB

There is a second device name for each device that uses Parallel Mode to access two SPI flashes in parallel. QSPI Flash programming support is provided through the following pin configs:

For the Renesas RZ A1H series device the following port pins are used to interface the (Q)SPI flash at channel 0 for single SPI:

Alternate function	Port / Pin
SPBCLK_0	P9_2
SPBSSL_0	P9_3
SPIO00	P9_4
SPIO10	P9_5
SPIO20	P9_6
SPIO30	P9_7

For the Renesas RZ A1H series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI:

Alternate function	Port / Pin
SPIO01	P2_12
SPIO11	P2_13
SPIO21	P2_14
SPIO31	P2_15

Watchdog Handling

The device has a watchdog that turned off during flash programming and turned back on afterwards if enabled.

Device specific handling

Reset

The device uses Cortex-A reset, no special handling necessary, like described here.