Renesas RA8P1

The Renesas RA8P1 are Cortex-M85 based microcontrollers with optional second Cortex-M33 core.

Flash Banks

Flash bank	Base address	J-Link support	Flasher support	Loader
				Name	Bank size
MRAM (Secure)	0x02000000			Default	up to 1 MB
				RAMLess	up to 1 MB
Configuration (Secure)	0x02C9F020			Default	976 B
OTP (Secure)	0x02E07400			Default	816 B
SiP flash (Secure)	0x08000000			Default	up to 8 MB
MRAM (Non-Secure)	0x12000000			Default	up to 1 MB
				RAMLess	up to 1 MB
Configuration (Non-Secure)	0x12C9F4C0			Default	832 B
OTP (Non-Secure)	0x12E07780			Default	128 B
SiP flash (Non-Secure)	0x18000000			Default	up to 8 MB
				RAMLess	up to 8 MB
External OSPI1 flash CS0	0x70000000			Default	up to 128 MB
External OSPI1 flash CS1	0x78000000			Default	up to 128 MB
External OSPI0 flash CS0	0x80000000			Default	up to 256 MB
External OSPI0 flash CS1	0x90000000			Default	up to 256 MB

Watchdog Handling

• The device has two watchdogs: Watchdog Timer (WDT) and Independent Watchdog Timer (IWDT).
• Both watchdogs are fed during flash programming.

Device Specific Handling

Connect

During connect the current security state of the device is determined. Depending on the state J-Link will use different RAM areas for operations that require RAM (flash programming, clock speed measurements):

• OEM_PL2: 0x220D0000-0x220DFFFF
• OEM_PL1: 0x320D0000-0x320DFFFF

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.

Device Initialization

Device initialization is implemented in the Device Provisioner utility: Renesas_RA8_Initialization.

Limitations

Using OEM_PL1 state with J-Flash

Since OEM_PL1 state requires the use of non-secure RAM (0x320D0000-0x320DFFFF), the user has to ensure that the J-Flash project is set up to use this RAM area instead of the secure RAM. By default J-Flash projects are created with secure RAM area (0x22060000-0x2206FFFF) selected.

Evaluation Boards

• Renesas EK-RA8P1

Example Application

• Renesas EK-RA8P1