Renesas RA8M2
The Renesas RA8M2 are Cortex-M85 based microcontrollers with optional second Cortex-M33 core.
Flash Banks
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| MRAM (Secure) | 0x02000000 |  |
|
Default | up to 1 MB |
| RAMLess | up to 1 MB | ||||
| Configuration (Secure) | 0x02C9F020 | |
|
Default | 976 B |
| OTP (Secure) | 0x02E07400 | |
|
Default | 816 B |
| SiP flash (Secure) [1] | 0x08000000 | |
|
Default | up to 8 MB |
| MRAM (Non-Secure) | 0x12000000 | |
|
Default | up to 1 MB |
| RAMLess | up to 1 MB | ||||
| Configuration (Non-Secure) | 0x12C9F4C0 | |
|
Default | 832 B |
| OTP (Non-Secure) | 0x12E07780 | |
|
Default | 128 B |
| SiP flash (Non-Secure) [1] | 0x18000000 | |
|
Default | up to 8 MB |
| External OSPI0 flash CS0 [2] | 0x80000000 | |
|
Default | up to 256 MB |
| External OSPI0 flash CS1 [2] | 0x90000000 | |
|
Default | up to 256 MB |
- ↑ 1.0 1.1 SiP flash only exists on the J-Variants of devices.
- ↑ 2.0 2.1
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Watchdog Handling
- The device has two watchdogs: Watchdog Timer (WDT) and Independent Watchdog Timer (IWDT).
- Both watchdogs are fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Evaluation Boards
- TBD
Example Application
- TBD
Tracing on Renesas RA8M2
This section describes how to get started with trace on the Renesas RA8M2 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
Some of the examples are shipped with a compiled .JLinkScriptfile (extension .pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracingMinimum requirements
In order to use trace on the Renesas RA8M2 MCU devices, the following minimum requirements have to be met:
- J-Link software version V9.48 or later
- Ozone V3.40c or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO version V3.0 or later for streaming trace
- J-Link Plus V12 or later for TMC/ETB trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V8.26c. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Cortex-M85
The project below has been tested with the minimum requirements mentioned above and a EK-RA8M2.
- Example project: Renesas_RA8M2_M85_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer (TMC/ETB)
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Cortex-M33
The project below has been tested with the minimum requirements mentioned above and a EK-RA8M2.
- Example project: Renesas_RA8M2_M33_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer (TMC/ETB)
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Tested Hardware
Specifics/Limitations
Some of the trace signals may be connected to other ICs which can lead to issues with signal integrity. So make sure to check your board revision and board reference manual if there are any solder bridges that might need to be set or cut to enable tracing for all 4 data pins.
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
