Renesas RA8M2
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The Renesas RA8M2 are Cortex-M85 based microcontrollers with optional second Cortex-M33 core.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| MRAM (Secure) | 0x02000000 | 
|
Default | up to 1 MB |
| RAMLess | up to 1 MB | |||
| Configuration (Secure) | 0x02C9F020 |
|
Default | 976 B |
| OTP (Secure) | 0x02E07400 |
|
Default | 816 B |
| SiP flash (Secure) [1] | 0x08000000 |
|
Default | up to 8 MB |
| MRAM (Non-Secure) | 0x12000000 |
|
Default | up to 1 MB |
| RAMLess | up to 1 MB | |||
| Configuration (Non-Secure) | 0x12C9F4C0 |
|
Default | 832 B |
| OTP (Non-Secure) | 0x12E07780 |
|
Default | 128 B |
| External OSPI0 flash CS0 [2] | 0x80000000 |
|
Default | up to 256 MB |
| External OSPI0 flash CS1 [2] | 0x90000000 |
|
Default | up to 256 MB |
- ↑ SiP flash only exists on the J-Variants of devices.
- ↑ 2.0 2.1
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Watchdog Handling
- The device has two watchdogs: Watchdog Timer (WDT) and Independent Watchdog Timer (IWDT).
- Both watchdogs are fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Evaluation Boards
- TBD
Example Application
- TBD