Renesas RA6M3

This article covers the Renesas RA6M3 Family

Flash Banks

Internal Flash

Flash bank	Base address	J-Link support	Flasher support	Loader
				Name	Bank size
Internal program flash	0x00000000			Default	Up to 2048 KB
Internal option-setting memory	0x0100A150			Default	32 B
Internal data flash	0x40100000			Default	64 KB

External QSPI flash

Flash bank	Base address	J-Link support	Flasher support	Loader
				Name	Bank size
External QSPI flash	0x60000000			CLK@P305_nCS@P306_D0@P307_D1@P308_D2@P309_D3@P310	Up to 64 MB
				CLK@P500_nCS@P501_D0@P502_D1@P503_D2@P504_D3@P505	Up to 64 MB
				CLK@P214_nCS@P207_D0@P211_D1@P210_D2@P209_D3@P208	Up to 64 MB

Other pin configurations are available on request. In such cases, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

Limitations

Security

• The device has a debug locking feature based on the 128 bit IDCODE, programmed into option-setting memory.
• During connection, the user will be asked to specify the IDCODE code to unlock debugging access if it was previously programmed.
• Use the following IDCODE to send the ALeRASE command, which triggers erasure of the user flash (code and data) area and the configuration area: FFFFFFFFFFFFFFFFFF45534152654C41
• Important: Make sure the byte order of the ALeRASE command is correct, as above shown above. A common mistake is using the wrong byte order, which will cause the command to fail.

Tracing on RA6M3 series

This section describes how to get started with trace on the Renesas RA6M3 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

• The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
• The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
• In order to rebuild the sample project, SEGGER Embedded Studio can be used.
• The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
  • To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Tracing on Renesas R7FA6M3AH3C

Minimum requirements

In order to use trace on the Renesas R7FA6M3AH3C MCU devices, the following minimum requirements have to be met:

• J-Link software version V6.62 or later
• Ozone V3.10c or later (if streaming trace and / or the sample project from below shall be used)
• J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
• J-Link Plus V10 or later for ETB trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

The project has been tested with the minimum requirements mentioned above and a Renesas EK-RA6M3 evaluation board.

Example project: Renesas_R7FA6M3AH_TracePins.zip

Trace buffer (ETB)

Example Project: Renesas_R7FA6M3AH_TraceBuffer.zip

Tested Hardware

Renesas EK-RA6M3

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time