PSoC Edge E8

The Infineon PSoC Edge E8 is a family of microcontrollers (MCUs) designed for edge-AI and machine-learning-enhanced sensing applications.

Flash Banks

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
RRAM_NS	0x02000000		Extended BOOT 40KB	388 KB
			Extended BOOT 60KB	368 KB
RRAM_S	0x12000000		Extended BOOT 40KB	388 KB
			Extended BOOT 60KB	368 KB
SMIF0	0x60000000		default	64 MB

Watchdog Handling

• The device includes two watchdogs: the Free-Running Watchdog Timer (WDT) and the Multi-Counter Watchdog.
• Both watchdogs are serviced during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The PSoC Edge E8 family comes with a variety of multi-core options.
The devices from this family feature the APPCPU which is disabled after reset / by default.

Core	J-Link Support
SYSCPU (CM33)
APPCPU (CM55)

Below, the debug related multi-core behavior of the J-Link is described for each core:

SYSCPU

Init/Setup

• Enables debugging

Reset

• Resets the core via a AIRCR.SYSRESETREQ and halts execution after the bootloader when a valid VTOR is detected.
• Skips the reset and sets the PC to a debug loop in the SRAM when no valid VTOR is detected.

Attach

• Attach is supported

APPCPU

Init/Setup

• The core is powered up and enabled via the SYSCPU.

Reset

• Resets the core via a system reset and halts execution after the bootloader when a valid VTOR is detected.
• Skips the reset and sets the PC to a debug loop in the CM55_ITCM when no valid VTOR is detected.

Attach

• Attach is supported with the J-Link Command String "ForceAttachTarget" option.

Limitations

Flash programming

• Flash programming is supported only via the SYSCPU, as the APPCPU does not have access to the peripheral registers.

RRAM

• RRAM is divided into multiple regions. Not all regions are programmable. Unsupported sectors must be deselected by the user, as they are device- and configuration-specific.
• The flash bank cannot be programmed from its base address, as the write-protected Extended BOOT area is located at the beginning of the flash.
• RRAM has two predefined loaders: “Extended BOOT 40KB” and “Extended BOOT 60KB”.
  • The loader will ignore and not program any data located in the Extended BOOT area, since this region is write-protected.
• If your Extended BOOT configuration differs from these two predefined loaders, it is the user’s responsibility to deselect the protected sectors to ensure that the loader does not attempt to modify data in this region.

Evaluation Boards

• Infineon PSOC Edge E8 Evaluation Kit

Example Application

• Infineon PSOC Edge E8 Evaluation Kit example project