Infineon PSoC Edge E8

The Infineon PSoC Edge E8 is a family of microcontrollers (MCUs) designed for edge-AI and machine-learning-enhanced sensing applications.

Flash Banks

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
RRAM_NS	0x22011000		default	Up to 356 KB
RRAM_S	0x32011000		default	Up to 356 KB
SMIF0_NS	0x60000000		default	64 MB
SMIF0_S	0x70000000		default	64 MB

Watchdog Handling

• The device includes two watchdogs: the Free-Running Watchdog Timer (WDT) and the Multi-Counter Watchdog.
• Both watchdogs are serviced during flash programming.

Reset

Device specific reset handling is added to this device series. The different available types are:

1. XRES pin: This is the most reliable reset source and cannot be blocked by software protection. The only practical limitation is when the XRES pin is not wired to the probe (for example, due to galvanic isolation or a limited pin count).
2. RES_SOFT_CTL.TRIGGER_SOFT: This software reset can be driven via the SYS-AP, which makes it preferable to SYSRESETREQ via M33-AP or M55-AP when those core APs may be closed by policy. It can be affected by PPC settings, but in practice, it often works in scenarios where core-specific accesses are blocked.
3. AIRCR.SYSRESETREQ: Functionally, this is quite close to XRES, but it is subject to AIRCR.SYSRESETREQS, so it may not be available if the core is running a restricted non-secure application.
4. AIRCR.VECTRESET: This only resets the current core. Actually, it is not real VECTRESET, as it is not available in ARMv8-M. This is a replacement that involves the CPUSS_CM33_CMD register. It does not guarantee a full device boot (or that all boot assets and security configuration are re-initialised). It can also be affected by PPC settings. Because of the limited scope, it is less suitable as an early “universal” reset attempt.
5. DP.CTRL/STAT.CDBGRSTREQ: This is the least desirable option and is intended as a last resort. If a standard software reset via SYSRESETREQ fails, that usually means the firmware has significantly altered the system (e.g. AHB-AP access disabled). If we still have access to the DAP, CDBGRSTREQ is the final try.

Per default the default reset handler will deciced which reset type to pick in which situation. However in some scenarios e.g. RAM debugging you might want to override the default behaviour and only select one specific reset type. For this command string SetResetType can be used.

M33 defaults

On the Cortex-M33 core types 1-5 are supported.

M55 defaults

On the Cortex-M55 core type 4 is supported.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The PSoC Edge E8 family comes with a variety of multi-core options.
The devices from this family feature the APPCPU which is disabled after reset / by default.

Core	J-Link Support
SYSCPU (CM33)
APPCPU (CM55)

Below, the debug related multi-core behavior of the J-Link is described for each core:

SYSCPU

Init/Setup

• Enables debugging

Reset

• Resets the core via a AIRCR.SYSRESETREQ and halts execution after the bootloader when a valid VTOR is detected.
• Skips the reset and sets the PC to a debug loop in the SRAM when no valid VTOR is detected.

Attach

• Attach is supported

APPCPU

Init/Setup

• The core is powered up and enabled via the SYSCPU.

Reset

• Resets the core via a system reset and halts execution after the bootloader when a valid VTOR is detected.
• Skips the reset and sets the PC to a debug loop in the CM55_ITCM when no valid VTOR is detected.

Attach

• Attach is supported with the J-Link Command String "ForceAttachTarget" option.

Limitations

Flash programming

• Flash programming is supported only via the SYSCPU, as the APPCPU does not have access to the peripheral registers.

RRAM

• RRAM is divided into multiple regions. Not all regions are programmable. Unsupported sectors must be deselected by the user, as they are device- and configuration-specific.

Evaluation Boards

• Infineon PSOC Edge E8 Evaluation Kit

Example Application

• Infineon PSOC Edge E8 Evaluation Kit example project