NXP i.MX RT1180
The NXP i.MXRT1180 (RT1180) series features a high performance Cortex-M7 core and a power efficient Cortex-M33 core.
Flash Banks
QSPI Flash
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| FlexSPI1 (NS)[1] | 0x28000000 |  |
|
PortA | Up to 128 MB |
| PortB[2] | Up to 128 MB | ||||
| FlexSPI1 (S)[1] | 0x38000000 | |
|
PortA | Up to 128 MB |
| PortB[2] | Up to 128 MB | ||||
| FlexSPI2 (NS)[1] | 0x04000000 | |
|
PortA | Up to 64MB |
| FlexSPI2 (S)[1] | 0x14000000 | |
|
PortA | Up to 64MB |
- ↑ 1.0 1.1 1.2 1.3
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for this Device. The default loader is marked in bold. For details on how to select a specific flash loader, please see here. - ↑ 2.0 2.1 For MIMXRT1182 devices the default loader for FlexSPI1 differs and is PortB.
J-Link supports one pin configuration for FlexSPI1 Port A and Port B:
| Port A | Port B | ||
|---|---|---|---|
| Signal | Pin | Signal | Pin |
| FlexSPI1_A_SCLK | GPIO_B2_08 | FlexSPI1_B_SCLK | GPIO_SD_B2_07 |
| FlexSPI1_A_SS0_B | GPIO_B2_09 | FlexSPI1_B_SS0_B | GPIO_SD_B2_06 |
| FlexSPI1_A_DATA0 | GPIO_B2_10 | FlexSPI1_B_DATA0 | GPIO_SD_B2_08 |
| FlexSPI1_A_DATA1 | GPIO_B2_11 | FlexSPI1_B_DATA1 | GPIO_SD_B2_09 |
| FlexSPI1_A_DATA2 | GPIO_B2_12 | FlexSPI1_B_DATA2 | GPIO_SD_B2_10 |
| FlexSPI1_A_DATA3 | GPIO_B2_13 | FlexSPI1_B_DATA3 | GPIO_SD_B2_11 |
J-Link supports one pin configuration for FlexSPI2 Port A.
| Port A | |
|---|---|
| Signal | Pin |
| FlexSPI2_A_SCLK | GPIO_AON_23 |
| FlexSPI2_A_SS0_B | GPIO_AON_22 |
| FlexSPI2_A_DATA0 | GPIO_AON_24 |
| FlexSPI2_A_DATA1 | GPIO_AON_25 |
| FlexSPI2_A_DATA2 | GPIO_AON_26 |
| FlexSPI2_A_DATA3 | GPIO_AON_27 |
Flash programming is supported via Cortex-M33 as well as Cortex-M7.
ECC RAM
ECC RAM needs to be initialized before it can be used. By default, the J-Link initializes RAM regions which are required for the initial connect to the target only. For the RT1180 series, the initialized regions depend on the selected core. For details, please refer to the sections below. Please note that reading to uninitialized regions result in ECC errors.
Watchdog Handling
- The device has five watchdogs WDOG1, WDOG2, WDOG3, WDOG4 and WDOG5.
- All watchdogs can be configured in normal or window mode.
- If it is configured in normal mode the watchdog is fed during flash programming.
- If it is configured in window mode the watchdog is fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The RT1180 family comes with a Cortex-M33 (main core) and a Cortex-M7 (secondary core). After reset / by default, the Cortex-M7 is disabled.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initiate the M33 System TCM RAM @ 0x20000000 (128 KB) which is used as work RAM during flash programming on connect.
Reset
- No reset is performed.
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the secondary core is not enabled yet:
- it will be enabled / released from reset
- The M33 System ITCM RAM @ 0x00000000 (128 KB) which is used as work RAM during flash programming on connect will be initialized
- If it's already enabled, a simple attach will be performed
Reset
- No reset is performed.
Attach
- Attach is supported / desired
Evaluation Boards
- NXP X-MIMXRT1180-EVK: NXP X-MIMXRT1180-EVK
- NXP FRDM-IMXRT1186: NXP_FRDM-IMXRT1186