NXP i.MX 8ULP
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The NXP i.MX 8ULP are embedded multi-core processors consisting of an Cortex-M33 and two Cortex-A35 cores.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8ULP family comes with a variety of multi-core options listed in the following table:
| Core | J-Link Support |
|---|---|
| Cortex-A35 core0 | 
|
| Cortex-A35 core1 | 
|
| 1 x Cortex-M33 |
|
| 1 x HIFI4 DSP |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A35 cores
Init/Setup
The cores are enabled after boot.
Reset
Core reset is not performed.
Cortex-M33 core
Init/Setup
The core is enabled after boot.