NXP MCX W

The NXP MCX W are single/dual core ARM Cortex-M33 microprocessors for wireless applications.

Flash Banks

Internal Flash (MCX W7x, dual core)

Flash Bank	Base address	Size	J-Link Support
Internal Flash(NS)	0x00000000	up to 2 MB
Internal Flash(S)	0x10000000	up to 2 MB
NBU Flash (via Core 0)	0x48800000	512 KB
NBU Flash (via Core 1)	0x00000000	512 KB

Internal Flash (MCX W23x, single core)

Flash Bank	Base address	Size	J-Link Support
Internal Flash(NS)	0x00000000	up to 1 MB
Internal Flash(S)	0x10000000	up to 1 MB

Watchdog Handling

• The device has 1 watchdog.
• The watchdog is fed during flash programming on Core 0.

ECC RAM

• J-Link initializes on connect to M33 Core 0 32KB RAM at address 0x30004000.
• No init is done on connect to M33 Core 1.

Note:
This section only applies to MCX W7x devices.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The MCX W7x family comes with a second NBU radio core (Core 1).
This is disabled after reset / by default.

Core	J-Link Support
M33 Core 0
M33 Core 1 (NBU / Radio)

In below, the debug related multi-core behavior of the J-Link is described for each core:

M33 Main core 0

Init/Setup

• Initializes the ECC RAM
• Enables debugging

Reset

• Device specific reset is performed.

Attach

• Attach is supported if attach mode is forced, details can be found here.

M33 secondary core 1 (NBU / Radio)

Init/Setup

• If debugging is not enabled yet, the secondary core executes the enable debug sequence.
• If the secondary core is not enabled yet, it will be enabled / released from reset-

Reset

• The core is reset via core 0 peripheral RF2P4GHZ_CTRL.

Attach

• Attach is supported.

Evaluation Boards

NXP X-FRDM-MCX W7x1 evaluation board

Example Application

NXP X-FRDM-MCX W7x1 evaluation board