NXP K32W0x2

The NXP K32W022, K32W032 and K32W042 series are 32 bit dual core devices with a Cortex-M4 core and a Cortex-M0 core.

Flash Banks

M0 core view

Flash Bank	Base address	Size	J-Link Support
Internal flash (M4 core)	0x00000000 - 0x000FFFFF	1024 KB
Internal flash (M0 core)	0x01000000 - 0x0103FFFF	256 KB

M4 core view

Flash Bank	Base address	Size	J-Link Support
Internal flash (M4 core)	0x00001000 - 0x000FFFFF	1020 KB
Internal flash (M0 core)	0x01000000 - 0x0103FFFF	256 KB

Watchdogs

The device has two watchdogs WDOG0 and WDOG1 that are fed during flash programming.

Device Specific Handling

Connect

On connect, the protection level is checked. If a secured device is detected, J-Link asks to unsecure the device by performing a mass erase.

Reset

The device uses Cortex-M Core reset, no special handling necessary, like described here.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.

The default boot core (after reset) can be selected / configured in the so called "Flash Option" register (FOPT) which is part of the flash memory module (FTFE). The flash memory module can be accessed through both cores. Per default, all bits in the FOPT are set to 1 which means that the Cortex-M4 core is selected as boot core (BOOT_CORE) and the boot source (BOOT_SRC) is set to boot from Boot ROM.

Boot ROM

By default, MCU will boot from Boot ROM, in this case, it will take about 30 seconds to execute ROM code before jump to application code, this will make user think the application code can’t be executed while indeed just need some patient to wait. Alternatively, the MCU can be configured to boot from the internal flash directly instead of executing the boot ROM prior. To do so, the two BOOT_SRC bits in the FTFE_FOPT register needs to be set to 0 (boot from internal flash). This can be done by issuing the Program Index command (0x43) with the index of the FOPT register (0x84) as parameter. The register needs to be set to 0xFFFFF3FF. Below, an example how to access (program, read, erase) the FOPT register through the flash module using the J-Link Commander, is given:

Program the FOPT register

//
// Program the FOPT register to 0xFFFFF3FF in order to set boot source to boot from internal flash (Cortex-M4)
// Please note that the new configuration will become active after power-on-reset, only
//
w1 0x40023007 0x43  // FCCOB0: CMD_PROGRAM_ONCE (IFR)
w1 0x40023006 0x84  // FCCOB1: IFR Index of the FOPT
w1 0x40023005 0x00  // FCCOB2: Not used
w1 0x40023004 0x00  // FCCOB3: Not used
w1 0x4002300B 0xFF  // FCCOB4: Record byte 0 value --> FOPT (Bit31:Bit24)
w1 0x4002300A 0xFF  // FCCOB5: Record byte 1 value --> FOPT (Bit23:Bit16)
w1 0x40023009 0xF3  // FCCOB6: Record byte 2 value --> FOPT (Bit15:Bit8)
w1 0x40023008 0xFF  // FCCOB7: Record byte 3 value --> FOPT (Bit7:Bit0)
w1 0x40023000 0x80  // Trigger operation

Read the FOPT register

w1 0x40023007 0x41  // FCCOB0: CMD_READ_IFR
w1 0x40023006 0x84  // FCCOB1: IFR Index of the FOPT
w1 0x40023000 0x80  // Trigger operation
mem8 0x4002300B 1   // FCCOB4: Record byte 0 value --> FOPT (Bit31:Bit24)
mem8 0x4002300A 1   // FCCOB5: Record byte 1 value --> FOPT (Bit23:Bit16)
mem8 0x40023009 1   // FCCOB6: Record byte 2 value --> FOPT (Bit15:Bit8)
mem8 0x40023008 1   // FCCOB7: Record byte 3 value --> FOPT (Bit7:Bit0)

Erase FOPT register (and flash content)

w1 0x40023007 0x44  // FCCOB0: CMD_ERASE_CHIP
w1 0x40023000 0x80  // Trigger operation