NUCLEO-F756ZG
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This article describes specifics for the ST NUCLEO-F756ZG evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | CN11 | 5 | VDD |
| GND | CN11 | 8 | GND |
| TMS/SWDIO | CN11 | 13 | PA13 |
| TCK/SWCLK | CN11 | 15 | PA14 |
| RESET | CN11 | 14 | RESET |
- Power the board via CN1
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ST NUCLEO-F756ZG.
It is a simple Hello World sample linked into the internal flash.
SETUP
- Embedded Studio: V8.26b
- Hardware: ST NUCLEO-F756ZG
- Link: File:ST NUCLEO-F756ZG TestProject ES V826b.zip