Infineon XMC5000
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The Infineon XMC5000 device family are multicore microcontrollers featuring a Cortex-M4 and Cortex-M0+ core.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Code flash | 0x10000000 | 
|
Default | Up to 840 KB |
| Work flash | 0x14000000 |
|
Default | Up to 80 KB |
| Supervisory flash | 0x17000800 |
|
Default | 6.5 KB |
Watchdog Handling
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
| Core | J-Link Support |
|---|---|
| Cortex-M0+ |
|
| Cortex-M4 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-M0+
Init/Setup
- Enables debugging
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Cortex-M4
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Attach
- Attach is supported / desired