Infineon TLE9870
The Infineon TL9870 series are microcontrollers with 3-phase bridge driver based on the ARM Cortex-M3 processor.
Flash Banks
TLE9871
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Code flash | 0x11000000 | 32KB | 
|
| Data flash | 0x11008000 | 4KB |
|
TLE9872
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Code flash | 0x11000000 | 252KB |
|
| Data flash | 0x1103F000 | 4KB |
|
TLE9873
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Code flash | 0x11000000 | 44KB |
|
| Data flash | 0x1100B000 | 4KB |
|
TLE9877
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Code flash | 0x11000000 | 60KB |
|
| Data flash | 0x1100F000 | 4KB |
|
TLE9879
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Code flash | 0x11000000 | 128KB |
|
| Data flash | 0x1101F000 | 4KB |
|
Watchdog Handling
The device has a watchdog that is fed during flash programming.
Device Specific Handling
Reset
The device uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
J-Link device selection in IDE
The device selection is mandatory to make sure that J-Link applies the correct connect and reset sequences to the TLE 9870 series devices. By selecting "generic Cortex-M3" correct functionality cannot be guaranteed. This is mainly because the TLE9870 series need a special connect sequence that makes sure that TCK/SWCLK and TMS/SWDIO are sampled with the correct values after reset, to enable the debug interface (JTAG/SWD).
Device readout protection
Once the readout protection of the device has been activated, it cannot be unprotected via the debug interface (JTAG/SWD) anymore. J-Link can still access the debug registers but not more. It is no longer possible to access any other memory through the debug interface or to issue halt requests etc. to the core (they will be ignored)
Low power modes
It is recommended to not enter low power modes during debug because this will lead to a connection loss. It is also recommended to wait at least 20ms after reset release before entering a low power mode. Otherwise J-Link may be unable to gain control over a already programmed device that is running a software that enters low power modes (which effectively disables debug access)
Reset pin
It is mandatory to connect the reset pin of the device to the J-Link debug connector. J-Link needs to be able to control the reset pin. Otherwise a proper connection to the device cannot be guaranteed.
Reset strategies
J-Link will always perform a reset of the core + peripherals via the AIRCR register and the reset pin. All other reset strategies that may be selectable in the IDE are ignored and will result in this reset strategy.