Infineon TLD4020
The Infineon TLD4020 are Cortex-M23 based LIN RGB driver MCUs.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x12000000 | 30 KB | 
|
| 1000 TP | 0x11FFFDC0 | 576 B |
|
ECC Flash
Device has ECC Flash, no special handling necessary.
Watchdog Handling
- The device has a window watchdog .
- The watchdog is disabled during debug connection by the device itself.
- The watchdog is not fed during flash programming.
Device Specific Handling
Maximum SWCLK speed
The maximum SWCLK is not defined, and the the device has a open drain output on SWDIO.
So the reachable speed mainly depends on the hardware design.
On the TLD4020-3STD_EVAL P00 board we achieved a speed of 1 MHz.
1000 TP Flash Bank
The programming of this area is done by the BOOTROM.
For this reason the device is reset several times during programming.
Connect
In order to set user debug mode, SWDIO and SWCLK have to be set high before powering the device.
This disables the watchdog and enables the debugging.
This is done by driving reset low (this interrupts device power on TLD4020-3STD_EVAL), seting SWDIO and SWCLK high
and then enable power for the device (reset = 1).
Disable of BSL and SWD interface
A J-Flash project for disabling the BSL and SWD interface can be downloaded here.
After successful programming first the BSL and second the SWD interface is disabled.
Note: Interface disabling is only working when a valid application is present in flash.
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- The device has no reset input, so the J-Link reset pin should be connected to a power interrupter circuit, which disables the device power while reset = 0.
Attach
Attach is not supported.