Infineon PSC3 (P7, P8, M7, M8)
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The Infineon PSC3 are Cortex-M33-based microcontrollers suitable for a wide range of secure applications.
Flash Banks
PSC3P7F, PSC3P8F, PSC3M7F, PSC3M8F
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| FLASH_NS | 0x22000000 |  |
|
FLASH_NS | 256 KB |
| FLASH_S | 0x32000000 | |
|
FLASH_S | 256 KB |
PSC3P7G, PSC3P8G, PSC3M7G, PSC3M8G
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| FLASH_NS | 0x22000000 | |
|
FLASH_NS | 512 KB |
| FLASH_S | 0x32000000 | |
|
FLASH_S | 512 KB |
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The PSC3 family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
| Core | J-Link Support |
|---|---|
| 1x Cortex-M33 Main core |
|
| 2x Cortex-M33 PPCA core |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- If a normal connect attempt fails, J-Link connects using Test Mode Acquisition sequence, see Test Mode Acquisition
Reset
- Device specific reset is performed, see Device Specific Handling
Attach
- Attach is supported
PPCA core(s)
Init/Setup
- If the PPCA core is not enabled yet, it will be enabled / released from reset during connect phase
- If a normal connect attempt fails, J-Link connects using Test Mode Acquisition sequence, see Test Mode Acquisition
Reset
- Device specific reset is performed, see Device Specific Handling
Attach
- Attach is supported
Restrictions
- J-Link Software uses 3rd party PPCA core debug support provided by Infineon.
Watchdog Handling
- The device has a watchdog WDT.
- The watchdog reset is disabled when the debugger is connected.
Device Specific Handling
Connect
- For connect J-Link implements a ConfigTargetSettings() which specifies the API map of the device. No other special handling is required.
Reset
- The device uses custom reset: Hardware pin reset, RESET(15) must be connected to function.
Test Mode Acquisition
If DAP is not accessible, it is possible that the user's firmware reconfigured the debug pins to be used as GPIO or disabled the debug port. In this case, J-Link tries to connect to the device in Test mode (TM).