Infineon PSC3 (P7, P8, M7, M8)

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The Infineon PSC3 are Cortex-M33-based microcontrollers suitable for a wide range of secure applications.

Flash Banks

PSC3P7F, PSC3P8F, PSC3M7F, PSC3M8F

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
FLASH_NS [1] 0x22000000 YES.png YES.png Default 256 KB
FLASH_S [2] 0x32000000 YES.png YES.png Default 256 KB
FLASH_DBM1_NS [2] 0x22800000 YES.png YES.png Default 128 KB
FLASH_DBM1_S [2] 0x32800000 YES.png YES.png Default 128 KB
  1. ↑ Enabled by default
  2. ↑ 2.0 2.1 2.2 Disabled by default

PSC3P7G, PSC3P8G, PSC3M7G, PSC3M8G

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
FLASH_NS [1] 0x22000000 YES.png YES.png Default 512 KB
FLASH_S [2] 0x32000000 YES.png YES.png Default 512 KB
FLASH_DBM1_NS [2] 0x22800000 YES.png YES.png Default 256 KB
FLASH_DBM1_S [2] 0x32800000 YES.png YES.png Default 256 KB
  1. ↑ Enabled by default
  2. ↑ 2.0 2.1 2.2 Disabled by default

Dual Bank Mode

  • The devices can be configured to operate in either single-bank or dual-bank mode.
  • For PSC3MxG, PSC3PxG devices, the 256 KB flash memory is split into two 128 KB banks in dual-bank mode.
  • For PSC3MxF, PSC3PxF devices, the 512 KB flash memory is split into two 256 KB banks in dual-bank mode.
  • When dual-bank mode is enabled, make sure to also enable the corresponding FLASH_DBM1_NS or FLASH_DBM1_S FlashBank.
  • The alternate bank is accessible at 0x22800000 through the non-secure alias and at 0x32800000 through the secure alias.

Flash Layout

PSC3MxG, PSC3PxG

Mode Start address Size Description
Dual-bank mode 0x22000000 128 KB Main bank
0x22800000 128 KB Alternate bank
Single-bank mode 0x22000000 256 KB Single bank

PSC3MxF, PSC3PxF

Mode Start address Size Description
Dual-bank mode 0x22000000 256 KB Main bank
0x22800000 256 KB Alternate bank
Single-bank mode 0x22000000 512 KB Single bank

Secure Debug

J-Link supports secure debug through Cortex-M33 (CM33) access port authentication. For more information, refer to Infineon PSC3 Secure Debug.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The PSC3 family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.

Core J-Link Support
1x Cortex-M33 Main core YES.png
2x Cortex-M33 PPCA core YES.png

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

  • If a normal connect attempt fails, J-Link connects using Test Mode Acquisition sequence, see Test Mode Acquisition

Reset

Attach

  • Attach is supported

PPCA core(s)

Init/Setup

  • If the PPCA core is not enabled yet, it will be enabled / released from reset during connect phase
  • If a normal connect attempt fails, J-Link connects using Test Mode Acquisition sequence, see Test Mode Acquisition

Reset

Attach

  • Attach is supported

Restrictions

  • J-Link Software uses 3rd party PPCA core debug support provided by Infineon.

Watchdog Handling

  • The device has a watchdog WDT.
  • The watchdog reset is disabled when the debugger is connected.

Device Specific Handling

Connect

  • For connect J-Link implements a ConfigTargetSettings() which specifies the API map of the device. No other special handling is required.

Reset

  • The device uses custom reset: Hardware pin reset, RESET(15) must be connected to function.

Test Mode Acquisition

If DAP is not accessible, it is possible that the user's firmware reconfigured the debug pins to be used as GPIO or disabled the debug port. In this case, J-Link tries to connect to the device in Test mode (TM).

Evaluation Boards

Example Application

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