FractionalDivider

A Fractional divider is a divider which is capable of dividing by non-integer values. It is used in hardware (silicon) as well as FPGAs to divide a frequency by non integer number.

How does a regular, non fractional divider work?

Regular, non-fractional dividers count edges on the input (either just leading or falling or both) and toggle the output every so and so often. The number of edges (events) they count is always the same, so that a constant input frequency with no jitter results in a constant output frequency with no jitter.

Example

If the input signal is 100MHz, the length of one clock is 10ns. If the signal is completely symmetric, the high phase lasts 5ns and the low phase last 5ns. 100MHz means the signal repeats 100 million times per second, so 100M rising edges and 100M falling edges. If the counter now only counts on one edge (typically rising edge), then only half the events are counted. If it divides by 1, but only uses one of the two edges (as a lot of HDL code does ("on rising edge"), the the output frequency is cut in half, so to 50MHz. So for a divider which uses only one edge, output frequency is InputFreq / 2*n. Such a divider would be able to deliver:

• 50MHz (n = 1, division by 2)
• 25MHz (n = 2, division by 4)
• 16.66MHz (n = 3, division by 6)

How does a fractional dividers work?

Very similar. Only that the divider has a fractional part which gets added up. So if the divider is 3.25, the output changes after 3, 3, 3 and the 4 events. So this way the output signal has jitter, but its average frequency is exactly 3.25 times less than the input frequency (assuming that both edges are counted ... if only one edge counts, it divides by 3.25 * 2)

Example

• 3.25
• 2.25
• 1.25
• 0.25 -> 3.50
• 2.50
• 1.50
• 0.50 -> 3.75
• 2.75
• 1.75
• 0.75 -> 4.00
• 3.00
• 2.00
• 1.00
• 0.00 -> 3.25