Espressif ESP32-C6

The ESP32-C6 family are RISC-V based microcontrollers.

Flash Banks

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
External QSPI Flash	0x4200_0000		-	-

Watchdog Handling

• The device has 4 watchdogs.
• The watchdogs are stopped during debugging.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
ESP32-C6 family feature a secondary low-power core which is disabled after reset.

Core	J-Link Support
HP_CPU
LP_CPU

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core(High-performance core)

Init/Setup

• No additional setup performed

Reset

• RISC-V normal reset is performed

Attach

• Attach is supported

Secondary core(Low-power core)

Init/Setup

• The core is reset before connect

Reset

• Specific reset is performed

Attach

• Attach is not supported

Device Specific Handling

Reset

• The device uses normal RISC-V reset, no special handling necessary, like described here.

Debugging ESP32

For some ESP32 devices, JTAG is disabled by default and depending on the project configuration a so called hardware stack protection is active. How to prepare everything to be ready for debugging is described here Debug Espressif ESP32

Evaluation Boards

• Espressif ESP32-C6-DevKitM-1

Example Application

• Espressif ESP32-C6-DevKitM-1#Example_Project