C*Core CCRC40XX
The C*Core CCRC40XX are multi-core microprocessors with advanced functional safety (ASIL-D) implementation based on the RISC-V CRV6 cores.
Supported devices
Refer to the supported device list for a full list of all supported CCRC40XX family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| JTAG |  |
|
NVM banks (RRAM)
CCRC4086S
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| UTest NVM (OTP) [1] | 0x00400000 | |
|
Default | 16 KB |
| HSM Code RRAM | 0x00600000 | |
|
Default | 512 KB |
| EEPROM RRAM | 0x00800000 | |
|
Default | 2048 KB |
| Data RRAM | 0x00F88000 | |
|
Default | 224 KB |
| HSM Data RRAM | 0x00FC0000 | |
|
Default | 256 KB |
| Internal RRAM 0 | 0x01000000 | |
|
Default | 4096 KB |
| Internal RRAM 1 | 0x01400000 | |
|
Default | 4096 KB |
| Internal RRAM 2 | 0x01800000 | |
|
Default | 4096 KB |
| Internal RRAM 3 | 0x01C00000 | |
|
Default | 4096 KB |
| Internal RRAM 4 | 0x02000000 | |
|
Default | 4096 KB |
| Internal RRAM 5 | 0x02400000 | |
|
Default | 4096 KB |
- ↑ Some of the bytes are already provisioned to the vendor. Refer to the reference manual on valid user addresses
RAM
The device features a total of 6 MB System RAM, which is ECC protected. The J-Link initializes a small area at the beginning. In addition each core have its own dedicated 128 KB ITCM and 512 KB DTCM RAM.
Watchdog handling
- The device has multiple watchdog named SWT.
- The watchdogs can be configured in normal or window mode.
- If it is configured in normal mode the watchdog is fed during flash programming.
- If it is configured in window mode the watchdog is fed during flash programming.
- If Fixed address feed or Incremental address feed is selected as mode the watchdog is not fed.
Device specific handling
Connect
Sample text (cross-link to multi-core)
Reset
- The device uses normal RISC-V core reset, no special handling necessary, like described here.
Attach
Attach is a debugging feature which exclusively applies to J-Link and J-Trace and does not apply to Flasher.
- Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Security
Multi-core support
Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Before proceeding with this article, please refer to the generic article regarding multi-core debugging here.
The CCRC40XX family comes with a variety of multi-core options. The CCRC4086S has six CRV6 RISC-V cores with six equivalent lockstep cores. The lockstep cores cannot be accessed. Additionally, the CCRC40XX family features an extra CRV6 core for security operations named the Hardware Security Module (HSM).
| Core | J-Link support |
|---|---|
| CRV6_0 |
|
| CRV6_1 | 
|
| CRV6_2 |
|
| CRV6_3 |
|
| CRV6_4 |
|
| CRV6_5 |
|
| CRV6_HSM |
|
Below the debug related multi-core behavior of the J-Link is described for each core:
CRV6_0 (Main core)
Init/Setup
- Initializes the ECC System-RAM and the core-specific ITCM/DTCM.
- Enables debugging
Reset
- Default reset is performed.
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default