Espressif ESP32-C5
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The ESP32-C5 family are RISC-V based microcontrollers.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| External QSPI Flash | 0x4200_0000 | 
|
- | - |
Watchdog Handling
- The device has 4 watchdogs.
- The watchdogs are stopped during debugging.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
ESP32-C5 family feature a secondary low-power core which is disabled after reset.
| Core | J-Link Support |
|---|---|
| HP_CPU | 
|
| LP_CPU |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core(High-performance core)
Init/Setup
- No additional setup performed
Reset
- Specific reset is performed
Attach
- Attach is supported
Secondary core(Low-power core)
Init/Setup
- The core is reset before connect
Reset
- Specific reset is performed
Attach
- Attach is supported
Device Specific Handling
Hardware stack protection
When debugging applications compiled with ESP-IDF framework, "SDK Config -> Component config -> ESP System Settings -> Hardware stack guard" option must be turned off to prevent core panic on writes to SP register(performed by J-Link logic).
Reset
The device uses normal RISC-V reset, no special handling necessary, like described here.