Infineon CYT4DN

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Revision as of 16:37, 30 June 2025 by Matthias (talk | contribs) (Matthias moved page Infineon CYT3DN to Infineon CYT4DN)
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The Infineon CYT3DN is a subfamily of Infineon Traveo T2G microcontrollers containing two Cortex M7 and Cortex M0+ CPU.

SRAM

The CYT3DN family features 640 KB of SRAM located at 0x28000000. The first 2 KB are reserved for internal usage and may not be used.

Flash memory layout

The CYT3DN series devices have 6336 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.

Flash Start adress End adress Sector size Sector count Total size
Code flash large area 0x10000000 0x105EFFFF 32 KiB 190 6080 KiB
Code flash small area 0x105F0000 0x1062FFFF 8 KiB 32 256 KiB
Work flash large area 0x14000000 0x14017FFF 2 KiB 48 96 KiB
Work flash small area 0x14018000 0x1401FFFF 128 B 256 32 KiB


Note:
For information regarding Supervisory Flash (SFlash), please refer to Infineon Traveo T2G article