Xilinx Zynq UltraScalePlus
The Xilinx Zynq UltraScale+ is a multi-processor system on chip, that contains up to 4 ARM Cortex-A53 application processor cores, 2 ARM Cortex-R5 real-time processor cores and user-programmagble logic (FGPA). It can optionally include ARM Mali-400MP2 graphical processor, H.264/H.265 Video Codec, RF and digital front-end subsystem.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The Zynq UltraScale+ family comes with a variety of multi-core options.
The device contains 2 Microblaze cores (CSU and PMU) that implements security and platform management features. These cores are responsible for boot and system configuration processes.
| Core | J-Link Support |
|---|---|
| 4x Cortex-A53 | 
|
| 2x Cortex-R5 |
|
| 1x Microblaze CSU | 
|
| 1x Microblaze PMU |
|
| 1x Mali GPU |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A53
Init/Setup
In order to connect to and debug one of the available Cortex-A53 on the UltraScale+ series, an UltraScale+ device with XCZU..._A53_n must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website.
Reset
When connecting to the Cortex-A53, J-Link will try to attach to a running target, otherwise it will reset the core and halt it via vector catch. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-A53 core it is connected to. No peripherals or other cores will be reset. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset.
Attach
Attach supported.
Cortex-R5
Init/Setup
In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with XCZU..._R5_n must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website. Dual/Split mode is supported only if not attaching to a running target.
Reset
When connecting to the Cortex-R5, J-Link will try to attach to a running target, otherwise it will reset the core and halt it via vector catch. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-A53 core it is connected to. No peripherals or other cores will be reset. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset.
Attach
Attach is supported.
Limitations
J-Link only supports JTAG-boot mode, as ARM DAP access can be enabled externaly. Cortex-A53 and Cortex-R5 are held in reset by default in this mode.
JTAG access to the ARM DAP is enabled by J-Link before connecting to the target.
J-Link supports only connection via the PS JTAG interface.
Example Application
The following projects are simple Hello world applications, loaded into the OCMRAM memory of the Zynq UltraScale+.