TI AM263Px
The TI AM263Px are Arm Cortex-R5F-based MCUs with up to 4 cores for real-time control, safety and security applications.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| QSPI Flash | 0x60000000 | 
|
QSPI_FLASH | 128 MB |
Restrictions
- QSPI controller can access 2 flash devices: connected to CS0 port and connected to CS1 port. Currently supported only CS0 port.
ECC RAM
- If the DevBoot mode is selected, TCMA RAM will be initialized for correct ECC operation during the connect phase.
Watchdog Handling
- The device has for watchdogs: WWDT0, WWDT1, WDT2 and WDT3: one for each core.
- During flash programming the only WWDT0(core 0) is fed, as the core should not access the watchdog of another core.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The AM263Px family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which function as a diagnostic core(Lockstep mode) by default.
The device may have multiple main cores (organized in clusters: main core + secondary core).
When connecting to a main core, it will be initialized if not already running.
When connecting to a secondary core, it will be switched to the Dual-core mode if not already running.
| Cluster | Core | Core type | J-Link Support |
|---|---|---|---|
| 0 | Arm Cortex-R5F_0 | Primary |
|
| Arm Cortex-R5F_1 | Secondary/Diagnostic |
| |
| 1 | Arm Cortex-R5F_2 | Primary |
|
| Arm Cortex-R5F_3 | Secondary/Diagnostic |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
If the core is not already running:
- Initializes the ECC TCMA RAM if DevBoot mode selected.
- Writes an infinite loop instruction to the default reset vector location(different for main cores).
- Starts the core.
If the core is already running:
- Attach is performed.
Reset
- In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a J-Link script file.
Attach
- Attach is supported.
Secondary core(s)
Init/Setup
If the core is in Lockstep mode:
- Initializes the ECC TCMA RAM if DevBoot mode selected.
- Writes an infinite loop instruction to the default reset vector location(0x00000000)
- Disables Lockstep mode.
If the core is in Dual-core mode:
- Attach is performed.
Reset
- No reset is performed.
Attach
- Attach is supported.
Device Specific Handling
Connect
Reset
- The device reset is not performed, as it requires multi-core and boot-loader handling.