NXP MCX E31

The NXP MCX E are Arm Cortex-M7 microprocessors.

Flash Banks

Internal Flash

Flash Bank	Base address	Size	J-Link Support
Code flash 0	0x00400000	Up to 1 MB
Code flash 1	0x00500000	Up to 1 MB
Code flash 2	0x00600000	Up to 1 MB
Code flash 3	0x00700000	Up to 1 MB
Data flash	0x10000000	Up to 128 KB

ECC RAM

The ITCM and DTCM must be properly initialized with correct ECC before any read operation to avoid any code runaway or software malfunction or core lockup. ITCM must be initialized with 64-bit writes whereas DTCM can be initialized with 32-bit or 64-bit writes. The following memory ranges are initialized by the J-Link on connect by default. Other ranges needs to be initialized by the application / boot ROM.

Memory	Address	Size
DTCM0	0x20000000	32 KB
SRAM0	0x20400000	16 KB

Reset

The J-Link performs a device specific reset sequence. The reset is executed for the main core, only. Reset of the main core, resets / disables the secondary core if used in parallel.

Note:
The reset pin needs to be connected in order to guarantee a proper reset.

Main core

Init/Setup

• Initializes the ECC RAM, see #ECC_RAM
• Enables debugging

Reset

• Device specific reset is performed, see #Reset

Attach

• Attach is not supported because the J-Link initializes certain RAM regions by default

Reset

The J-Link performs a device specific reset sequence.

Note:
The reset pin needs to be connected in order to guarantee a proper reset.

Evaluation Boards

• TBD

Example Application

• TBD