Syntacore SCR4: Difference between revisions
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= Requirements = | == Requirements == | ||
* A current J-Link model with RISC-V support | * A current J-Link model with RISC-V support | ||
* [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V7.84g or later | * [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V7.84g or later | ||
* The SCR4 device selection is supported since V7.84g | * The SCR4 device selection is supported since V7.84g | ||
= RTT support = | == RTT support == | ||
As the core does not support System Bus Access (SBA), RTT is '''not''' supported for this core. | As the core does not support System Bus Access (SBA), RTT is '''not''' supported for this core. | ||
= HSS access = | == HSS access == | ||
As the core does not support System Bus Access (SBA), HSS is '''not''' supported for this core. | As the core does not support System Bus Access (SBA), HSS is '''not''' supported for this core. | ||
= Limitations = | == Limitations == | ||
* When debugging, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. '''This is not a limitation of J-Link but of the core''' | * When debugging, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. '''This is not a limitation of J-Link but of the core''' | ||
Latest revision as of 18:02, 6 December 2024
The Syntacore SCR4 is a 32-bit (RV32) or 64-bit (RV64) core, designed by Syntacore.
Requirements
- A current J-Link model with RISC-V support
- J-Link software V7.84g or later
- The SCR4 device selection is supported since V7.84g
RTT support
As the core does not support System Bus Access (SBA), RTT is not supported for this core.
HSS access
As the core does not support System Bus Access (SBA), HSS is not supported for this core.
Limitations
- When debugging, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. This is not a limitation of J-Link but of the core