Arria 10 SoC Development Kit

Connecting J-Link to Altera Arria 10 SoC Development Kit

There are multiple connectors on the Altera Arria 10 board that allow J-Link connection. Note that only J24 is enabled by default:

Connector	Description
J24	Via Intel FPGA Adapter
J20 (FPGA TRACE)	Via J-Link Mictor 38 Adapter
J43 (HPS TRACE)	Via J-Link Mictor 38 Adapter

Here is the pin config between JTAG connector(J24) on the evalboard and the J-Link debug emulator:

JTAG(J24)          J-Link
1  (TCK)     <-->  9  (TCK)
2  (ENABLEN) <-->  6  (GND)
3  (TCK)     <-->  13 (TDO)
4  (3V3)     <-->  1  (VTref)
5  (TMS)     <-->  7  (TMS)
6  (RSTn)    <-->  15 (RESET)
9  (TDI)     <-->  5  (TDI)
10 (GND)     <-->  4  (GND)

Deviating from the default settings SW3 on the needs the following setting, so only the Arria 10 device is in the JTAG chain:

SW3
1  (Arria 10)  -->  OFF (default) Arria10 JTAG Enable
2  (I/O MAX V) -->  ON  (changed) MAXV JTAG Bypass
3  (FMCA)      -->  ON  (default) FMCA JTAG Bypass
4  (FMCB)      -->  ON  (default) FMCB JTAG Bypass
5  (PCIe)      -->  ON  (default) PCIe JTAG Bypass
6  (MSTR[0])   -->  OFF (default)
7  (MSTR[1])   -->  OFF (default)
8  (MSTR[2])   -->  OFF (default)

A successful connection should look like this:

• 

Tracing on Altera Arria 10

This section describes how to get started with trace on the Altera Arria 10 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

Some of the examples are shipped with a compiled .JLinkScriptfile (extension .pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Minimum requirements

In order to use trace on the Altera Arria 10 MCU devices, the following minimum requirements have to be met:

• J-Link software version V8.10d or later
• Ozone V3.38 or later (if streaming trace and / or the sample project from below shall be used)
• J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
• J-Link Plus V12 or later for TMC/ETB trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V8.18. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

The project below has been tested with the minimum requirements mentioned above and a Arria 10 SoC Development Kit.

• Example project: Altera_Arria10_TraceExample.zip

Streaming trace

Open the *_TracePins.jdebug project contained in the example project in Ozone.

Trace buffer (TMC/ETB)

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Tested Hardware

Arria 10 SoC Development Kit

Specifics/Limitations

Above trace example was tested with the Golden System Reference Design (GSRD) installed onto the SD Card.

For pin tracing via J43 (HPS TRACE) change the SW3 settings as follows:

SW3
1  (Arria 10)  -->  OFF (default) Arria10 JTAG Enable
2  (I/O MAX V) -->  ON  (changed) MAXV JTAG Bypass
3  (FMCA)      -->  ON  (default) FMCA JTAG Bypass
4  (FMCB)      -->  ON  (default) FMCB JTAG Bypass
5  (PCIe)      -->  ON  (default) PCIe JTAG Bypass
6  (MSTR[0])   -->  ON  (changed) Enable HPS TRACE
7  (MSTR[1])   -->  ON  (changed)        -"-
8  (MSTR[2])   -->  ON  (changed)        -"-

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time