Nations N32H78x: Difference between revisions
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(Created page with "Category:Device families The '''Nations N32H78x''' are Cortex-M7 (up to 600MHz) + Cortex-M4 (up to 300MHz) based MCUs with a rich set of peripherals. __TOC__ ==Flash Banks== ===N32H78xxI=== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankName=Main flash | BaseAddress=0x15000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= {{:Template:FlashLoader | Name=Default | Size=2 MB }} }} }} ===N32H78xxK=== {{:Template:FlashBankTable | FlashBanks...") |
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==Watchdog Handling== | ==Watchdog Handling== | ||
*The device has | *The device has two independent watchdogs: IWDG and two windowed watchdogs: WWDG. | ||
*The watchdogs are stopped during flash programming. | *The watchdogs are stopped during flash programming. | ||
| Line 63: | Line 63: | ||
==Evaluation Boards== | ==Evaluation Boards== | ||
*[[Nations_N32H785XxB7EC_STB|Nations N32H785XxB7EC_STB]] | *[[Nations_N32H785XxB7EC_STB|Nations N32H785XxB7EC_STB]] | ||
*[[Nations_N32H785XIB7_STB|Nations N32H785XIB7_STB]] | |||
*[[Nations_N32H787XKB7_STB|Nations N32H787XKB7_STB]] | |||
==Example Application== | ==Example Application== | ||
*[[Nations_N32H785XxB7EC_STB#Example_Project | Nations N32H785XxB7EC_STB]] | *[[Nations_N32H785XxB7EC_STB#Example_Project | Nations N32H785XxB7EC_STB]] | ||
Latest revision as of 13:49, 27 August 2025
The Nations N32H78x are Cortex-M7 (up to 600MHz) + Cortex-M4 (up to 300MHz) based MCUs with a rich set of peripherals.
Flash Banks
N32H78xxI
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Main flash | 0x15000000 | 
|
Default | 2 MB |
N32H78xxK
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Main flash | 0x15000000 |
|
Default | 4 MB |
Watchdog Handling
- The device has two independent watchdogs: IWDG and two windowed watchdogs: WWDG.
- The watchdogs are stopped during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The N32H78x family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| Cortex-M7 |
|
| Cortex-M4 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- A Boot-ROM API function is executed to determine RDP protection level and the user is prompted to perform RDP regression (erases flash memory content and removes readout protection).
Reset
- Device specific reset is performed: the core is stopped using the breakpoint unit after the Cortex-M system reset.
Attach
- Attach is not supported because the J-Link executes Boot-ROM API functions during initialization.
Secondary core(s)
Init/Setup
- A Boot-ROM API function is executed to determine RDP protection level and the user is prompted to perform RDP regression (erases flash memory content and removes readout protection).
Reset
- Device specific reset is performed using custom core reset.
Attach
- Attach is not supported because the J-Link executes Boot-ROM API functions during initialization.
Device Specific Handling
Option bytes programming
Limitations
Security
- Device supports readout protection (RDP). If a RDP1 level protected device is detected, the user will be prompted to unsecure the device.