GigaDevice GD32C1: Difference between revisions

From SEGGER Knowledge Base
Jump to navigation Jump to search
No edit summary
 
(5 intermediate revisions by one other user not shown)
Line 1: Line 1:
[[Category:Device families]]
The GigaDevice GD32C1 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor.
The GigaDevice GD32C1 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor.
__TOC__
__TOC__
Line 8: Line 9:
! Flash Bank || Base address !! Size || J-Link Support
! Flash Bank || Base address !! Size || J-Link Support
|-
|-
| Main flash || 0x08000000 || Up to 256 KB || style="text-align:center;"| {{YES}}
| Main flash || 0x08000000 || 128 KB || style="text-align:center;"| {{YES}}  
|-
| Information flash || 0x1FFFB000|| 18 KB || style="text-align:center;"| {{NO}}  
|-
|-
| Option Bytes  || 0x1FFFF800 || 16 B || style="text-align:center;"| {{YES}}  
| Option Bytes  || 0x1FFFF800 || 16 B || style="text-align:center;"| {{YES}}  
|-
|-
| OTP || 0x1FFF7000 || 512 B || style="text-align:center;"| {{NO}}  
| OTP Bytes || 0x1FFF7000 || 512 B || style="text-align:center;"| {{NO}}  
|}
|}


==On-Chip Memory Regions==
==Watchdog Handling==
The internal flash is divided into 4 different regions:<br>
*The device does have 2 watchdogs, FWDGT and WWDGT.
*Main Flash Block (0x08000000 - 0x0801FFFF)
*The WWDGT watchdog is fed during flash programming.
*Information Block (0x1FFFB000 - 0x1FFFF7FF)
*Option bytes Block (0x1FFFF800 - 0x1FFFF80F)
*One-time program Block (0x1FFF7000 - 0x1FFF71FF)


For now, the Main Flash Block is supported, only.
==Device Specific Handling==
===Connect===
*On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]].


==Reset==
===Reset===
No special reset is required.
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].


==Evaluation Boards==
==Evaluation Boards==
*GigaDevice GD32C113C-START: https://wiki.segger.com/GigaDevice_GD32C113C-START
*[[GigaDevice_GD32C113C-START| GigaDevice GD32C113C START]]


==Example Application==
==Example Application==
*GigaDevice GD32C113C-START: https://wiki.segger.com/GigaDevice_GD32C113C-START#Example_Project
*[[GigaDevice_GD32C113C-START#Example_Project | GigaDevice GD32C113C START]]

Latest revision as of 14:22, 15 May 2024

The GigaDevice GD32C1 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
Main flash 0x08000000 128 KB YES.png
Option Bytes 0x1FFFF800 16 B YES.png
OTP Bytes 0x1FFF7000 512 B NO.png

Watchdog Handling

  • The device does have 2 watchdogs, FWDGT and WWDGT.
  • The WWDGT watchdog is fed during flash programming.

Device Specific Handling

Connect

  • On Connect, protection level is checked. For further information regarding this, please click here.

Reset

  • The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

Example Application