J-Link EDU: Difference between revisions

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(Created page with "This page contains the general, specifications as well as an overview of supported software features of the SEGGER '''J-Link EDU'''. <br> For information on the mechanical and electrical specifications as well as an overview of hardware features refer to Hardware Models. __TOC__ == Hardware Models == * J-Link EDU Mini V1 === Legacy === * J-Link EDU V5 or lower * J-Link EDU V6 * J-Link EDU V7 * J-Link EDU V8 * J-Link EDU V9...")
 
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|| CMSIS-DAP V1(HID) mode                    ||style="text-align:center;"| {{NO}}  ||  
|| CMSIS-DAP V1(HID) mode                    ||style="text-align:center;"| {{NO}}  ||  
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|| CMSIS-DAP V2(Bulk) mode                    ||style="text-align:center;"| {{NO}}  ||
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|| USB Web SerV1                              ||style="text-align:center;"| {{NO}}  ||  
|| USB Web SerV1                              ||style="text-align:center;"| {{NO}}  ||  

Revision as of 16:13, 24 July 2025

This page contains the general, specifications as well as an overview of supported software features of the SEGGER J-Link EDU.
For information on the mechanical and electrical specifications as well as an overview of hardware features refer to Hardware Models.

Hardware Models

Legacy

Software Features

Feature Supported since
USB 2.0 Full Speed YES.png Mini V1
USB 2.0 Hi-Speed NO.png
WinUSB NO.png
JTAG interface YES.png Mini V1
cJTAG interface YES.png Mini V1
cJTAG interface without/buggy KEEPER logic YES.png Mini V1
SWD interface YES.png Mini V1
SWO interface YES.png Mini V1
SPI interface NO.png
QSPI interface NO.png
Microchip ICSP interface NO.png
Renesas FINE interface NO.png
SiLabs C2 2-wire interface NO.png
ETB Trace ARM7/9 NO.png
ETB Trace Cortex-M YES.png Mini V1
ETB Trace Cortex-A/R NO.png
ETM Trace Cortex-M NO.png
VCOM* NO.png
Memory Stop mode support YES.png Mini V1
Cortex-M Monitor Mode debugging NO.png
SWD Multi-Drop NO.png
CMSIS-DAP V1(HID) mode NO.png
CMSIS-DAP V2(Bulk) mode NO.png
USB Web SerV1 NO.png
Notes:
*On J-Links, VCOM is a "USB to serial" bridge that connects the PC to a UART of the target, so you can communicate with your target application.

Supported cores

J-Link provides debugging support for the following cores.

Note:
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
Core Supported Since
ARM legacy Cores
ARM7 NO.png
ARM9 NO.png
ARM11 NO.png
ARM Cortex Cores
Cortex-A5 YES.png Mini V1
Cortex-A7 YES.png Mini V1
Cortex-A8 YES.png Mini V1
Cortex-A9 YES.png Mini V1
Cortex-A12 YES.png Mini V1
Cortex-A15 YES.png Mini V1
Cortex-A17 YES.png Mini V1
Cortex-A53 YES.png Mini V1
Cortex-A55 YES.png Mini V1
Cortex-A57 YES.png Mini V1
Cortex-A72 YES.png Mini V1
Cortex-M0 YES.png Mini V1
Cortex-M0+ YES.png Mini V1
Cortex-M1 YES.png Mini V1
Cortex-M3 YES.png Mini V1
Cortex-M4 YES.png Mini V1
Cortex-M7 YES.png Mini V1
Cortex-M23 YES.png Mini V1
Cortex-M33 YES.png Mini V1
Cortex-M52 YES.png Mini V1
Cortex-M55 YES.png Mini V1
Cortex-M85 YES.png Mini V1
Cortex-R4 YES.png Mini V1
Cortex-R5 YES.png Mini V1
Cortex-R8 YES.png Mini V1
SC000 (M0 secure) YES.png Mini V1
SC300 (M3 secure) YES.png Mini V1
RISC-V
RV32 YES.png Mini V1
RV64 YES.png Mini V1
Microchip PIC32
PIC32MX NO.png
PIC32MZ NO.png
SiLabs 8051
EFM8 NO.png
Renesas RX
RX110 NO.png
RX111 NO.png
RX140 NO.png
RX210 NO.png
RX21A NO.png
RX220 NO.png
RX610 NO.png
RX621 NO.png
RX62G NO.png
RX62G NO.png
RX62N NO.png
RX62T NO.png
RX630 NO.png
RX631 NO.png
RX63N NO.png
RX63T NO.png
RX64M NO.png
RX660 NO.png
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