GigaDevice GD32A5: Difference between revisions
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[[Category:Device families]] | |||
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® | |||
Cortex®-M33 processor. | |||
__TOC__ | __TOC__ | ||
==Flash Banks== | |||
==Internal | ===Internal Flash=== | ||
{| class="seggertable" | {| class="seggertable" | ||
|- | |- | ||
! | ! Flash Bank || Base address !! Size || J-Link Support | ||
|- | |- | ||
| | | Main flash Bank 0 || 0x08000000 || Up to 256 KB || style="text-align:center;"| {{YES}} | ||
|- | |- | ||
| | | Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} | ||
|- | |- | ||
| Data flash || 0x08800000 || up to 64 KB || style="text-align:center;"| {{YES}} | |||
|- | |- | ||
| | | Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} | ||
|- | |- | ||
| | | Option Byte 1 || 0x40022068|| 4 B || style="text-align:center;"| {{YES}} | ||
|- | |- | ||
| | | OTP Bytes || 0x1FFF7000 || 1 KB || style="text-align:center;"| {{NO}} | ||
|} | |} | ||
<br> | |||
{{Note|After changing Option Byte 1, a power on reset has to be performed.}} | |||
==ECC RAM== | |||
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM | |||
starting at 0x2000 0000. | |||
== | ==Watchdog Handling== | ||
*The device does have 2 watchdogs. | |||
*The watchdogs are fed during flash programming. | |||
==Device Specific Handling== | |||
===Connect=== | |||
* On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]]. | |||
== | |||
===Reset=== | |||
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. | |||
==Evaluation Boards== | ==Evaluation Boards== | ||
*GigaDevice GD32A503-EVAL | *[[GigaDevice_GD32A503-EVAL|GigaDevice GD32A503-EVAL]] | ||
==Example Application== | ==Example Application== | ||
* | *[[GigaDevice_GD32A503-EVAL#Example_Project | GigaDevice GD32A503-EVAL]] | ||
Latest revision as of 10:21, 22 May 2024
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash Bank 0 | 0x08000000 | Up to 256 KB | 
|
| Main flash Bank 1 | 0x08040000 | 128 KB |
|
| Data flash | 0x08800000 | up to 64 KB |
|
| Option Byte 0 | 0x1FFFF800 | 24 B |
|
| Option Byte 1 | 0x40022068 | 4 B |
|
| OTP Bytes | 0x1FFF7000 | 1 KB | 
|
Note:
After changing Option Byte 1, a power on reset has to be performed.
After changing Option Byte 1, a power on reset has to be performed.
ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.