GigaDevice GD32A5: Difference between revisions
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| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} | | Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} | ||
|- | |||
| Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} | |||
|} | |} | ||
==ECC RAM== | ==ECC RAM== | ||
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM | In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM | ||
starting at 0x2000 0000. | starting at 0x2000 0000. | ||
== | ==Watchdog Handling== | ||
*The device does have 2 watchdogs. | |||
*The watchdogs are fed during flash programming. | |||
== | ==Device Specific Handling== | ||
===Connect=== | |||
== | ===Reset=== | ||
* J- | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. | ||
==Evaluation Boards== | ==Evaluation Boards== | ||
*GigaDevice GD32A503-EVAL | *[[GigaDevice_GD32A503-EVAL|GigaDevice GD32A503-EVAL]] | ||
==Example Application== | ==Example Application== | ||
* | *[[GigaDevice_GD32A503-EVAL#Example_Project | GigaDevice GD32A503-EVAL]] | ||
Revision as of 11:56, 15 February 2024
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash Bank 0 | 0x08000000 | Up to 256 KB | 
|
| Main flash Bank 1 | 0x08040000 | 128 KB |
|
| Option Byte 0 | 0x1FFFF800 | 24 B |
|
ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.