View source for Silicon Labs EFR32xG23

[[Category:Device families]]
The Silicon Labs '''EFR32xG23''' device family are Cortex-M33 based microcontrollers.
These MCUs are part of the [[Silicon Labs EFx32 Series 2 | EFx32 Series 2]] devices.

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== EFx32 Series 2 specifics ==
Please refer to the [[Silicon Labs EFx32 Series 2]] article.

==Flash Banks==
===Internal Flash===
{| class="seggertable"
|-
! Flash Bank     || Base address !! Size || J-Link Support
|-
| Internal flash || 0x0800_0000  || Up to 512 KB || style="text-align:center;"| {{YES}}
|-
| User Data      || 0x0FE0_0000  ||         1 KB || style="text-align:center;"| {{YES}}
|}

==Watchdog Handling==
The device has a watchdog, which is fed during flash programming, if enabled.

== Device Specific Handling ==
===Reset===
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].

=== Security ===
See: [[Silicon Labs EFx32 Series 2#Debug lock | Silicon Labs EFx32 Series 2]] article.

=== Secure boot ===
See: [[Silicon Labs EFx32 Series 2#Secure boot specific | Silicon Labs EFx32 Series 2]] article.

==Evaluation Boards==
*[[Silicon Labs BRD4210A]]

==Example Application==
*[[Silicon Labs BRD4210A#Example_Project|Silicon Labs BRD4210A]]

==Tracing on EFR32ZG23xxx series ==
This section describes how to get started with trace on the SiLabs EFR32ZG23xxx MCUs.
This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.).
If this is not the case, we recommend to read [[UM08001_J-Link_/_J-Trace_User_Guide#Trace | Trace]] chapter in the J-Link User Manual (UM08001).

'''Note:'''
* The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
* The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
* In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used.
* The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
** To create your own .JLinkScriptfile you can use the following guide as reference: [[How_to_configure_JLinkScript_files_to_enable_tracing]]


=== Tracing on SiLabs EFR32ZG23xxx ===
==== Minimum requirements ====
In order to use trace on the ST EFR32ZG23xxx MCU devices, the following minimum requirements have to be met:
* J-Link software version V7.88h or later
* Ozone V3.30 or later (if streaming trace and / or the sample project from below shall be used)
* J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

==== Streaming trace ====
The project has been tested with the minimum requirements mentioned above and a ''SiLabs BRD4204C Rev 00 Board'' on a ''PCB4001 Rev 03 motherboard''.

'''Example project:''' [[Media:SiliconLabs_EFR32ZG23_TracePins.zip | SiliconLabs_EFR32ZG23_TracePins.zip]]

==== Reference trace signal quality ====
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project.
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes.
If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project.
More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website].

===== Trace clock signal quality =====
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
[[File:SiLabs_EFR32ZG23_Multiple_TCLK.png|none|thumb|Trace clock signal quality]]
===== Rise time =====
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1.
For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
[[File:SiLabs_EFR32ZG23_RiseTime_TCLK.png|none|thumb|TCLK rise time]]

===== Setup time =====
The setup time shows the relative setup time between a trace data signal and trace clock.
The measurement markers are set at 50% of the expected voltage level respectively.
The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
[[File:SiLabs_EFR32ZG23_SetupTime_TD0.png|none|thumb|TD0 setup time]]