View source for SemiDrive D32xx

[[Category:Device families]]
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The SemiDrive D32xx are Cortex-R5 based MCUs.

==Internal Flash==

D32xx devices consist of a SIP and have an internal QSPI flash.

Therefore programming the internal flash requires special handling. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].

{| class="seggertable"
|-
! Flash Bank || Base address !! Size || J-Link Support
|-
| Main flash || 0x10000000 || Up to 4 MB || style="text-align:center;"| {{YES}} 
|}

==ECC RAM==
D32xx devices have ECC RAM which can be disabled.
However, a connect to D32xx devices will initialize 1MB at 0x400000.

==Reset==
No device specific reset is necessary. The normal Cortex-R reset is performed.

See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices