View source for NXP S32K3xx

[[Category:Device families]]
__TOC__
The S32K3 family from NXP includes Cortex-M7 based MCUs in single or dual core configurations supporting ASIL B/D safety applications. The S32K3 family is supported since J-Link software version V6.89c.
==Internal Flash==
===Supported Regions===
====S32K310====
{| class="seggertable"
|-
! Flash Bank    || Base address !! Size         || J-Link Support
|-
| Code flash 0  || 0x00400000   || Up to 512 KB || style="text-align:center;"| {{YES}}
|-
| Data flash    || 0x10000000   || Up to  64 KB || style="text-align:center;"| {{YES}}
|-
| UTEST         || 0x1B000000   || Up to  8 KB || style="text-align:center;"| {{NO}}
|}
{{Note|1=AB_SWAP configuration is not supported for the S32K310 yet.}}

====S32K311====
{| class="seggertable"
|-
! Flash Bank    || Base address !! Size         || J-Link Support
|-
| Code flash 0  || 0x00400000   || Up to 512 KB || style="text-align:center;"| {{YES}}
|-
| Code flash 1  || 0x00480000   || Up to 512 KB || style="text-align:center;"| {{YES}}
|-
| Data flash    || 0x10000000   || Up to  64 KB || style="text-align:center;"| {{YES}}
|-
| UTEST         || 0x1B000000   || Up to  8 KB || style="text-align:center;"| {{NO}}
|}

====S32K312, S32K322 and S32K342====
{| class="seggertable"
|-
! Flash Bank    || Base address !! Size         || J-Link Support
|-
| Code flash 0  || 0x00400000   || Up to 1 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 1  || 0x00500000   || Up to 1 MB   || style="text-align:center;"| {{YES}}
|-
| Data flash    || 0x10000000   || Up to 128 KB || style="text-align:center;"| {{YES}}
|-
| UTEST         || 0x1B000000   || Up to  8 KB || style="text-align:center;"| {{NO}}
|}

====S32K314, S32K324 and S32K344====
{| class="seggertable"
|-
! Flash Bank    || Base address !! Size         || J-Link Support
|-
| Code flash 0  || 0x00400000   || Up to 1 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 1  || 0x00500000   || Up to 1 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 2  || 0x00600000   || Up to 1 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 3  || 0x00700000   || Up to 1 MB   || style="text-align:center;"| {{YES}}
|-
| Data flash    || 0x10000000   || Up to 128 KB || style="text-align:center;"| {{YES}}
|-
| UTEST         || 0x1B000000   || Up to  8 KB || style="text-align:center;"| {{NO}}
|}

====S32K358 and S32K388====
{| class="seggertable"
|-
! Flash Bank    || Base address !! Size         || J-Link Support
|-
| Code flash 0  || 0x00400000   || Up to 2 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 1  || 0x00600000   || Up to 2 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 2  || 0x00800000   || Up to 2 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 3  || 0x00A00000   || Up to 2 MB   || style="text-align:center;"| {{YES}}
|-
| Data flash    || 0x10000000   || Up to 128 KB || style="text-align:center;"| {{YES}}
|-
| UTEST         || 0x1B000000   || Up to  8 KB || style="text-align:center;"| {{NO}}
|}
====S32K396====
{| class="seggertable"
|-
! Flash Bank    || Base address !! Size         || J-Link Support
|-
| Code flash 0  || 0x00400000   || Up to 2 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 1  || 0x00600000   || Up to 2 MB   || style="text-align:center;"| {{YES}}
|-
| Code flash 2  || 0x00800000   || Up to 2 MB   || style="text-align:center;"| {{YES}}
|-
| Data flash    || 0x10000000   || Up to 128 KB || style="text-align:center;"| {{YES}}
|-
| UTEST         || 0x1B000000   || Up to  8 KB || style="text-align:center;"| {{NO}}
|}

==ECC RAM==
The ITCM and DTCM must be properly initialized with correct ECC before any read operation to avoid any code runaway or software malfucntion or core lockup. ITCM must be initialized with 64-bit writes whereas DTCM can be initialized with 32-bit or 64-bit writes. The following memory ranges are initialized by the J-Link on connect by default. Other ranges needs to be initialized by the application / boot ROM.

{| class="seggertable"
|-
! Memory !! Address !! Size
|-
| DTCM0 || 0x20000000 || 32 KB
|-
| SRAM0 || 0x20400000 || 16 KB
|}

{{Note|1=Initialization of the work RAM is skipped in case the attach feature of J-Link is used (''exec ForceAttachTarget=1'')}}

==HSE activated==
In case of HSE firmware is installed, there are two configurations:
*FULL_MEM (code flash is considered as one region)
*AB_SWAP (code flash is split into two regions)
In case of FULL_MEM, the HSE is located at the end of the last code flash memory. Access to this region is prohibited.<br>
In case of AP_SWAP is used, the code flash will be split into two regions. In this case, the HSE is available twice (once per region) and located at the end of both regions.

==Multi-Core Support==
Before proceeding with this article, please check out the generic article regarding [[Multi-Core_Debugging | Multi-Core Debugging]].<br>
The S32K3 family comes with a variety of multi-core options. Usually co-processors are disabled after reset / by default thus needs to be enabled by the J-Link on connect. Some of them are running in permanent ''lockstep'' mode, some are operating in optional lockstep mode and others are pure single core co-processors. In below, the debug related multi-core behavior of the J-Link is described for each core:
===Main core (Cortex-M7_0) ===
====Init/Setup====
*Initializes the ECC RAM, see [[NXP_S32K3xx#ECC_RAM | ECC RAM]]
*Enables debugging
====Reset====
*Device specific reset is performed, see [[NXP_S32K3xx#Reset | Reset]]
====Attach====
*By default, the ECC RAM is initialized thus attach is not possible. In order to attach to the target, the ''exec ForceAttachTarget=1'' command string needs to be used.

===Secondary cores (Cortex-M7_1, Cortex-M7_2, Cortex-M7_3)===
====Init/Setup====
*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
*If the secondary core is not enabled yet, it will be enabled / released from reset
*Initializes the ECC RAM, see [[NXP_S32K3xx#ECC_RAM | ECC RAM]]

====Reset====
No reset is performed.
====Attach====
*Attach is supported / desired. Note that the ECC RAM will be initialized anyhow. In order to skip the ECC RAM init, the ''exec ForceAttachTarget=1'' command string needs to be used.

==Reset==
The J-Link performs a device specific reset sequence. The reset is executed for the main core, only. Reset of the main core, resets / disables the secondary core if used in parallel.
{{Note|1=The reset pin needs to be connected in order to guarantee a proper reset.}}
==Debug Authentication==
The S32K3xx family supports different security mechanisms. The following table provides an overview of which types are supported and which are not:
{| class="seggertable"
|-
! Silicon type || Info || J-Link Support
|-
| E5 || Configured for Secure boot assist flash (SBAF) || style="text-align:center;"| {{YES}}
|-
| E6 || Configured for secure application debug with password authentication. || style="text-align:center;"| {{YES}}
|-
| E7 || Configured for secure application debug with challenge/response authentication. || style="text-align:center;"| {{NO}}
|}

Depending on the authentication level, debug access can be granted if the correct key is passed. How this is possible is described below. 
===Specifying the authentication code using J-Link Command String===
This is the recommended method as the specified authentication key will be used for the whole session. This way, the key must not specified multiple times (e.g. if a reset is performed). The J-Link Command String needs to be passed to the J-Link DLL before establishing the target connection. The J-Link Command String [[J-Link_Command_Strings#SetCPUConnectIDCODE | SetCPUConnectIDCode <AuthKey>]] has to be used (see example below).

Example authentication key:
*AuthenticationKey0: 0x01234567
*AuthenticationKey1: 0x89ABCDEF
*AuthenticationKey2: 0x00224466
*AuthenticationKey3: 0x88AABBCC

  exec SetCPUConnectIDCODE 67452301EFCDAB8966442200CCBBAA88

===Specifying the authentication code using the ID Code dialog===
If the authentication key has not been specified using the Command String although it is required to enable debug access, the following message box will pop up which allows specifying the authentication key.

[[File:JLink_RZT2M_AuthenticationDialog.png]]

==Limitations==
=== Security / Authentication ===
There are three different types available in regard to the security. The following table provides an overview of which types are supported and which are not:
{| class="seggertable"
|-
! Silicon type || Info || J-Link Support
|-
| E5 || Configured for Secure boot assist flash (SBAF) || style="text-align:center;"| {{YES}}
|-
| E6 || Configured for secure application debug with password authentication. || style="text-align:center;"| {{YES}}
|-
| E7 || Configured for secure application debug with challenge/response authentication. || style="text-align:center;"| {{NO}}
|}

===SystemView===
With J-Link software V7.84e ECC RAM handling was added. So it is no longer possible to run a debug session in parallel with SystemView, as the connect from SystemView will reinitialize the ECC RAM init and overwrite the RTT buffers.
To avoid this the following .JLinkScript file must be added to SystemView.

[[Media:S32K3xx_SystemView.JLinkScript | S32K3xx_SystemView.JLinkScript]]

How to add a .JLinkScript to SystemView is explained here: [[J-Link_script_files#SystemView]]

==Evaluation Boards==
*NXP S32K3X4EVB-Q257 evaluation board: https://wiki.segger.com/NXP_S32K3X4EVB

==Example Application==
*NXP S32K3X4EVB evaluation board: https://wiki.segger.com/NXP_S32K3X4EVB#Example_Project
{{Note|1=The example has been tested on the S32K3X4EVB but it should run on any S32K344 based hardware.}}

== Tracing on NXP S32K344 ==
=== Minimum requirements ===
In order to use trace on the NXP S32K344 MCU devices, the following minimum requirements have to be met:
* J-Link software version V7.70c or later
* Ozone V3.26h or later (if streaming trace and / or the sample project from below shall be used)
* J-Trace PRO (for Cortex-M) HW version V1.0 or later for streaming trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

=== Streaming trace ===
The project has been tested with the minimum requirements mentioned above and the following two eval board:

* '''S32K3X4EVB-Q257''': [[Media:NXP_S32K344_TracePins.zip | NXP_S32K344_TracePins.zip]]

* '''S32K3X4EVB-T172''': [[Media:NXP_S32K344_S32K3X4EVB_TracePins.zip | NXP_S32K344_S32K3X4EVB_TracePins.zip]]

=== Trace buffer (TMC/ETB) ===
The project below is utilizing the on-chip trace buffer (it is not meant for streaming trace) and works with any NXP S32K344 board.

* '''Example project''': [[Media:NXP_S32K344_TraceBuffer.zip | NXP_S32K344_TraceBuffer.zip]]

=== Tested Hardware ===
[[File:NXP_S32K3X4EVB.jpeg|none|thumb|NXP S32K3X4EVB-Q257]]
[[File:s32k344_T172.jpg|none|thumb|NXP S32K3X4EVB-T172]]

=== Specifics/Limitations ===
The S32K3X4EVB_T172 needs some solder bridges closed and resistors removed for all 4 trace data pins to work. For more information about this see the board specific schematics.

=== Reference trace signal quality ===
The following pictures show oscilloscope measurements of trace signals output by the NXP S32K3X4EVB-Q257 using the example project.
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes.
If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project.
More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website].

==== Trace clock signal quality ====
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
[[File:S32K344_Multiple_TCLK.png|none|thumb|Trace clock signal quality]]

==== Rise time ====
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1.
For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
[[File:S32K344_Risetime_TCLK.png|none|thumb|TCLK rise time]]

==== Setup time ====
The setup time shows the relative setup time between a trace data signal and trace clock.
The measurement markers are set at 50% of the expected voltage level respectively.
The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
[[File:S32K344_Setuptime_TD0.png|none|thumb|TD0 setup time]]

{{:Template:EvalBoardTraceDefault
| Vendor=NXP
| Device=S32K388
| BoardName=XS32K388CVB-Q289
| JlinkVersion=V8.10b
| OzoneVersion=V3.38
| StudioVersion=V8.18
| TestedHw=yes
| TestedHwPic=XS32K388CVB-Q289.png
| PinTraceClk=S32K388_Multiple_TCLK.png
| PinTraceRise=S32K388_RiseTime_TCLK.png
| PinTraceSetup=S32K388_SetupTime_TD0.png
| Heading=
| TraceEx=NXP_S32K388_TraceExample.zip
| PinTrace=yes
| BufTrace=yes
| Optional=
}}